Senior Full-Chip Physical Verification Engineer
AnySilicon
Broadcom is seeking a senior ASIC verification engineer to join its sign-off flows team in San Jose. You will focus on physical verification, ESD checking, and package RDL routing, driving LVS/DRC/ANT/ERC checks and rule-deck debugging.
The role requires extensive full-chip verification experience and strong scripting skills with Perl, Tcl, or C shell to automate flows and debug issues across Cadence and Synopsys tools.
#J-18808-LjbffrVacancy posted 1 day ago
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