ASIC Design Verification Engineer

To ensure the functional correctness and performance of AI inference ASICs, the remote ASIC Design Verification Engineer will develop and execute advanced verification methodologies, collaborate with design teams, and lead the creation of verification environments using SystemVerilog UVM. Key Responsibilities Develop and execute verification strategies for AI inference ASICs Lead the development of verification environments and maintain simulation testbenches Collaborate with design and architecture teams to ensure functional coverage and closure Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 8+ years of experience in ASIC verification Expertise in SystemVerilog UVM and simulation tools Strong knowledge of verification planning and testbench development Experience with industry-standard EDA tools (Cadence, Synopsys, Mentor Graphics)