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Optical DSP Engineer (New Grad - Masters, PhD, Post Doc)

$79k - $126k

Ciena Corporation

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We're a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact.

How You Will Contribute:

Reporting to Senior Manager, DSP Engineering, as an Optical Systems Engineer, you will be part of the Signal Processing Team that works on the cutting edge of modem technology. You will be involved in the development, modeling, testing, and customer support for current and next generation high speed optical modems.

  • You will develop realistic models for complex channels and for impairment mitigating signal processing algorithms.
  • You will run simulations and document results in order to verify functions and algorithms.
  • You will provide detailed explanations and justifications for design trade-offs.
  • You will evaluate and optimize design alternatives with respect to relevant performance metrics.
  • You will perform code development in MATLAB according to generally accepted coding standards.
  • You will provide feedback/suggestions on existing designs and contribute ideas to improve design procedures.
  • You will write general specifications, test- and verification plans
  • You will test and verify final hardware functionality in the lab.
  • You will review customer-reported issues and partner with the software design team and subject matter experts from other groups to determine the path forward and/or identify potential improvements.

The Must Haves:

  • Masters or PhD degree in Engineering with focus on digital signal processing and/or communication systems and/or control systems or equivalent experience.
  • Experience working with MATLAB
  • Knowledge of modem building blocks such as DAC/ADC, amplifiers, analog and digital IIR/FIR filters, equalizers and feedback control loops.
  • Comfortable in ESD protected lab environment; familiar with standard lab equipment such as oscilloscopes, signal generators, network analyzers, power supplies, and spectrum analyzers.

Nice to Haves:

The following are not must-haves but desirable

  • Knowledge of optical communication systems
  • Exposure to optical communications lab environment
  • Design environment knowledge: Linux, Git (Bitbucket), Jira/Confluence and Microsoft Office.

Pay Range:

The annual pay range for this position is $79,000 - $126,000

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is anEqual Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Vacancy posted 1 day ago
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