ASIC STA Engineer: Timing & IP Integration
Apple Inc.
A leading technology company in Austin is seeking an ASIC STA Engineer to oversee timing closure and collaborate with SOC teams. Candidates should possess a Bachelor's degree and have strong fundamentals in digital design. Proficiency in scripting languages such as TCL, Python, and Perl is preferred. This role offers the chance to work on innovative projects that impact millions of customers daily and contribute to hardware technology transformation. #J-18808-Ljbffr Apple Inc.
- ...technology company in Austin, Texas, is looking for an ASIC STA Engineer to spearhead IP development. This role requires leading coordination with multiple SOC teams, executing integration tasks, and developing timing verification methodologies. Candidates should possess...Suggested
- A leading technology company in Austin, Texas is looking for an ASIC STA Engineer to take ownership of full chip and block level timing closure for SOC designs. Candidates must have a Bachelor's degree combined with 10 years of experience, and strong skills in digital design...Suggested
$100k
...Static Timing Analysis (STA) Methodology Engineer Austin, Texas, United States; Fort Collins, Colorado, United... ...timing challenges across multiple IPs and products. This role is hybrid... ...constraints. Best practices for integrating data-driven and ML-assisted approaches...SuggestedPermanent employment- A leading technology company in Austin is seeking an ASIC STA Engineer to manage timing constraints throughout the SoC design process. Responsibilities include timing sign-off, developing STA flows, and collaboration with various teams to ensure timing closure. Ideal candidates...Suggested
- ...searching for a hardworking engineer to join our exciting... ...for leading edge IP development and coordinating... ...to execute design and integration tasks for the high quality... .... Description As an ASIC STA Engineer, you will have... ...various aspects of SOC Timing: Full chip and block level...Suggested
- NVIDIA AI in Austin, TX is looking for an ASIC Design Engineer to join its System-On-Chip group. In this role, you will focus on improving methodologies and deliver system-level IP for performance measurement on cutting-edge GPUs and SOCs. The ideal candidate should have...
$168k - $264.5k
Senior ASIC RTL Integration and Netlisting Engineer page is loaded## Senior ASIC RTL Integration and Netlisting Engineerlocations: US, CA, Santa Clara: US... ...of Physical Design flows, design constraints, timing and power convergence* Proficiency in programming/scripting...$2,000 per month
...than a B200. With Etched ASICs, you can build products... ...with GPUs, like real-time video generation models... ...and staffed by leading engineers, Etched is redefining the... ...to join our Interface IP DV team. You will work... ...specifications. Collaborate with integration and SoC DV teams to...Work at officeRelocation packageShift work- Silicon Validation Software Engineer- GPU IP Validation and Integration Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture...
- A leading semiconductor company in Austin is seeking an ASIC Design Verification Engineer to enhance the development of cutting-edge technologies. The... ...architects, manage verification processes, and ensure high-quality IP delivery. Applicants should have a background in...
$141.91k - $269.1k
# **Welcome!**## .IP Methodology and Automation Engineer page is loaded## IP Methodology and Automation Engineerlocations... ...power, performance, area, and timing in physical design constraints.*... ...(MPP/UPF) designs.* Support the integration of new tools and methods into...Local areaImmediate startShift work$100k
...seeking an experienced Field Application Engineer to champion our revolutionary RISC-V CPU and AI accelerator IP products with customers worldwide. You will... ...in CPU IP. ~ Hands-on expertise with ASIC design flows, IP integration, and relevant design views (.lib, LEF, ICL...Permanent employmentWork at officeWorldwide- ...want to utilize your engineering background to make... ...state‑of‑the‑art ASICs. We have an extraordinary... ...the opportunity to integrate and come up with... ...for digital IP designers and/or users... ...optimize design flows and timing / power... ...and debug tools, and STA tools. Knowledge of...
- ...seeking an experienced SoC Physical Design Engineer to lead the physical implementation of... ...create scripts, and conduct deep analysis of timing paths. Ideal candidates will have... ...TCL, alongside a solid understanding of STA methodologies. #J-18808-Ljbffr Apple Inc.
$168k - $264.5k
SOC IP Methodology Engineer - Custom SOC page is loaded## SOC IP Methodology Engineer... ...to final design closure (timing and layout) involving... ...requirements for QA, smooth integration, and high-quality analysis... ...will also work with external ASIC companies if we decide to...- As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Develop and maintain... ..., process variations and signal integrity related issues is a plus Ability...Full time
$106.5k - $162k
...receive an alert: Senior Engineer, Physical Design (ASIC/SoC Place & Route) (Austin... ...floorplan, place and route, CTS, STA, and signoff. You will be... ...Route Implement ECOs for timing closure Signal EM/Noise... ...implementation or chip integration and signoff Experience in...Work at office- ...Description As a Cellular ASIC Design Engineer, you'll develop and... ...methodology for integrated circuits across multiple... ...products at the block/IP-level and system-level... ...synthesis, place-and-route, timing closure, and signoff... ...validation and STA vs spice correlation-...
- Description As an ASIC STA Engineer, you will have responsibilities spanning... ...aspects of SoC design in terms of timing. Key responsibilities include... ...development, ownership of IP and block level timing... ...process variations and signal integrity related issues. Hands on experience...
$116k - $189.75k
...NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus... ...and delivering system-level IP to measure performance across multiple... ...characteristic protected by law.* Be an integral part of the team defining, developing,...- .## ASIC Design Verification EngineerAustin,Texas,United States##... ...’s Stock Purchase Plan.**Your Time** Your work-life balance is important... ....At Ericsson, the ASICs our IP teams build are the backbone... ...— and the verification engineers who prove they work are the last...Temporary workWorldwide
$170k - $285k
...Digital Verification Engineers with a strong... ...of high-speed, real-time data-processing silicon... ...to ensure correct integration across clock domains... ...high-performance ASICs or SoCs Ownership... ...linting, CDC/RDC, STA, power-intent (UPF/... ...verifying high-speed IP such as SerDes, DDR...Permanent employmentTemporary workWork at officeLocal areaRelocationVisa sponsorship$2,000 per month
...latency than a B200. With Etched ASICs, you can build products that... ...with GPUs, like real-time video generation models and extremely... ...investors and staffed by leading engineers, Etched is redefining the... ...Engineer to join our Internal IP DV team. You will ensure the custom...Work at officeRelocation packageShift workNight shift- .## ASIC RTL Design EngineerAustin,Texas,United... ...Plan.**Your Time** Your work-life balance... ...***ASIC RTL Design Engineer** Hybrid work... ...Ericsson Silicon's ASIC IP organization is a... ...across 3rd-party IP integration, RTL design, simulation... ...timing analysis (STA) Hands-on...Temporary work
- ...Senior Digital Design Engineer, you will translate... ...system‑level integration and lab testing. You... ...implementation, and timing closure), iterating... ...cleanly from FPGA to ASIC. Responsibilities... ...analog/mixed‑signal IP, including ADC/DAC... ...flows (synthesis, STA, lint, CDC/RDC). Strong...
$130.45k - $142.38k
...information, please visit We Do: The Senior IP Telephony Engineer is responsible for the engineering,... ...AudioCodes), dial plans, and carrier integrations.Lead or materially contribute to... ...Support contact center telephony routing, time-of-day/holiday changes, and call...Local areaRemote work- ...Graphics FE Integration Engineer Do you intrinsically see the importance in... ...GPU RTL by integrating various IPs following architectural... ...synthesis, physical design and STA. Experience with RTL analysis... ...design integration issues in a timely manner. Ability to solve...
$136k - $218.5k
Senior STA Flow Engineer page is loaded## Senior STA Flow Engineerlocations: US, CA, Santa Clara:... ...the world.We are seeking an innovative Timing Methodology Engineer to help drive multi... ...ETM models, both of std cells and custom IPs.* Develop flows/recommendations on STA sign...- ...developing reliable, high-performance real-time systems using contemporary automotive-... ...a pragmatic team that prioritizes sound engineering and collaborative effort. About the... ...hardware architecture, figuring out how these integrated systems will function together. This is...Remote workRelocation
- ...Principal Mixed Signal Engineer, Texas Institute for Electronics... ...in 3D heterogeneous integration (3DHI), chiplet-based... ...paid vacation, sick time, and holidays* Teachers... ...innovations into IP roadmaps and reference... ...circuit design for SoC/ASIC, with direct involvement...Ongoing contractWork at officeMonday to FridayFlexible hoursShift work
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