Timing Design Engineer

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign‑off, STA and sign‑off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign‑off to achieve sign‑off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign‑off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis. Minimum Qualifications Bachelors of Science in Electrical Engineering. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and methodology. 2+ years of experience in writing ASIC timing constraints and timing closure. Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues. Hands on experience in timing/SDC constraints generation and management. Proficient in scripting languages (Tcl and Perl). Familiarity with synthesis, DFT and backend related methodology and tools. Strong communication skills are a pre‑requisite – you will be collaborating with many diverse groups at Apple. The ideal candidate will be a self‑starter and highly motivated to be successful at Apple. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. #J-18808-Ljbffr Apple Inc.