SoC Physical Design Methodology Engineer

SoC Physical Design Methodology Engineer In this role, you will be directly involved in our physical design methodology efforts, collaborating right alongside our internal multi‑functional teams to ensure our SoCs achieve the optimal power, performance, and area (PPA) in the most efficient way possible. You will create and implement methodologies that improve the robustness, power, performance, and area (PPA) of our on‑chip interconnects. You will perform electrical analysis to understand how physical effects impact the performance of our designs. You will develop construction methodologies to help mitigate any PPA degradation found in silicon. You will help ensure our modeling of silicon is efficient and accurate by running our sign‑off flows and comparing results to measurements from silicon we create. You will collaborate with the standard cell team to identify new cells to improve PPA, yield, or engineering productivity. You will work with CAD and design teams to drive these improvements and updates in our production design flows in an effective and timely manner. You will verify theories by creating a strategy to verify them in silicon and apply the latest advances in data science and machine learning when needed in crafting these methodologies. Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Science, or related field with 3 years of experience. Preferred Qualifications Strong intellectual curiosity, with excellent communication skills. Organized, a self‑starter, and adaptable to any challenge that comes up. Physical design experience on SoC designs is a plus. Experience working with advanced technology nodes. Deep knowledge about interconnects, parasitic extraction, performance analysis, and how manufacturing effects make these non‑ideal. Extensive knowledge of power delivery and how power‑supplies noise impacts chip performance. Understanding inductance effects and circuit design experience. Comfortable running and modifying Spice simulations. Familiar with static timing analysis tools and methodologies and able to explain silicon behaviors. Proven understanding of scripting languages such as Python and Tcl. Experience with flow development for a large number of users on a tight schedule is a plus. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EOO rights as an applicant. #J-18808-Ljbffr Apple Inc.