CPU Physical Design Engineer

Overview Join Intel’s CPU development team as a Physical Design Engineer, contributing to the design of core IP that powers cutting‑edge compute processors across client, server, IoT, and AI markets. Responsibilities Perform physical design implementation of custom CPU designs from RTL to GDS, creating a manufacturing‑ready design database. Conduct all aspects of the CPU physical design flow, including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Perform verification and sign‑off activities such as formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyze results and recommend improvements to current and future CPU microarchitectures while collaborating with logic, circuit, architecture, and design automation teams. Maintain expertise in structural and physical design areas such as physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement and routing, synthesis, and DFT. Work with industry EDA vendors to develop and enhance tool capabilities for high‑speed, low‑power synthesizable CPUs. Optimize CPU design for improved product‑level metrics (power, frequency, area). Participate in developing and refining physical design methodologies and flow automation. Qualifications Minimum Qualifications: Bachelor’s in Computer Engineering, Electrical Engineering or related field with 3+ years of relevant work experience, or M.S. with 2+ years of relevant experience. 2+ years of experience in synthesis of a digital logic block or partition. 2+ years in each of: integrated circuit design tools (Synopsys/Cadence) including logic synthesis, place and route, static timing analysis, design closure; PV convergence (timing and power analysis); chip physical design verification (formal equivalence, DRC/LVS, noise flow); TCL scripting. Preferred Qualifications: Knowledge of physical design best practices: floor‑planning, routing techniques, clock distribution. 1+ completed tape‑out on advanced technologies. Knowledge of static timing analysis, noise analysis, and reliability verification techniques. Experience with RTL to GDS methodologies and formal equivalence. CPU‑level timing analysis and optimization, ensuring functional and performance requirements are met. Experience generating and verifying timing constraints, addressing violations at chip or block level for CPU cores. Collaboration with clocking team and full‑chip designers to balance timing fixes, power delivery, clocking, and partitioning. Benefits Competitive compensation, stock bonuses, health, retirement, and vacation benefits. Annual salary range: $105,650 – $200,340 USD. Additional benefits details are available on Intel’s careers site. Work Model On‑site presence required. Shift 1 (United States of America), Primary location: Austin, Texas, United States. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr Intel Corporation