Senior CPU Physical Design Engineer

Job Details: Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. The Role As a CPU Physical Design Engineer, you will be a vital member of Intel's E-Core/Atom microprocessor design team, shaping the future of high-performance CPUs. This role offers the opportunity to work on cutting‑edge technology, solving complex design challenges, and optimizing CPU designs to deliver industry‑leading performance‑per‑watt solutions. Your work will directly contribute to driving innovation, enabling advanced computing platforms, and supporting Intel's mission to enrich the lives of every person on earth. Key Responsibilities Qualify and validate new PDK versions, standard cell libraries using backend design environment for RTL2GDS (Synthesis & APR) and custom verification flows. Conduct verification and sign‑off processes, including formal equivalence verification, static timing analysis, reliability verification, and physical verification tasks such as DRC/LVS, noise analysis, and electro‑migration checks. Manage internal Design Data Management repositories used by the design teams. Execute all aspects of the CPU physical design flow, including synthesis, floor planning, place and route, static timing analysis, power analysis, reliability, and noise analysis to maintain a stable design environment. Collaborate closely with cross‑functional teams—logic, circuit, and design automation—to improve current and future CPU microarchitectures. Work alongside industry EDA vendors to enhance tool capabilities and methodologies for designing high‑speed, low‑power CPUs. Participate in the development and improvement of physical design methodologies and flow automation processes. Develop scripts to automate design implementation stages, verification tasks, and quality analysis. Minimum Qualifications Bachelor's degree in Computer Engineering or Electrical Engineering or similar discipline with 5+ years of relevant experience, or Master's degree with 3+ years of relevant experience. 6+ years of experience in physical design and verification tools such as Synopsys Fusion Compiler, Cadence Genus/Innovus, Primetime, or similar industry‑standard tools. 4+ years of experience in performing regression tests and validation of PDKs, standard cell libraries, and backend tools. 4+ years of hands‑on experience with scripting languages such as TCL, Perl, or Python, and source‑code management. 2+ years of experience in design database management using Perforce, Git, and other database management tools. Preferred Qualifications Demonstrated expertise in CAD tools and design environment for chip‑level physical design verification, electrical rule checking, and static timing analysis for worst‑case corners. Familiarity with machine learning techniques for design optimization and problem solving, and expertise in leveraging co‑pilot (VScode) for design analysis, debugging, and software development. Effective communication skills and a collaborative mindset to work across diverse teams and geographies. A continuous learning attitude and strong analytical capabilities to tackle complex design challenges. Job Type & Information Experienced Hire. Shift 1 (United States of America). Primary Location: US, Texas, Austin. Additional Locations: Business group: Silicon and Platform Engineering Group (SPE). EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Compensation Annual salary range for US locations: $141,910.00–269,100.00 USD. Work Model This role will be eligible for a hybrid work model, allowing employees to split their time between working on‑site at their assigned Intel site and off‑site. #J-18808-Ljbffr Intel Corporation