RISC-V CPU Power & Clock Design Engineer
SiFive
A pioneering tech company in Austin, Texas, is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer. This role involves designing industry-leading CPU cores and subsystems focused on RISC-V technology. The ideal candidate will have over 3 years of experience in CPU designs, proficiency in hardware design with Verilog/SystemVerilog, and a collaborative mindset. The position includes a competitive pay package and benefits like health insurance and flexible time off. #J-18808-Ljbffr SiFive
Vacancy posted 20 hours ago
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