Senior Power Integrity Co-Design Engineer

Senior Power Integrity Co-Design Engineer – The SCG Architecture team is hiring an engineer to architect and deliver voltage‑noise mitigation across silicon, package, board, and platform. The role bridges architecture, silicon, and platform engineering, translating product noise targets into specifications and feeding silicon findings back into the next generation’s build. Responsibilities Architect voltage‑noise mitigation across the full stack and own the codesign trade‑offs between silicon, package, board, and platform. Co‑design noise features with Speed, Power, Reliability, Circuit Design, Power‑Arch, ASIC, and platform teams. Define product‑level voltage noise targets, drive them to closure, and sign them off at shipment. Build and own the Sim‑to‑Si correlation methodology for noise. Model and prototype next‑gen noise features – transient sense, droop response, mitigation IP – and codify them for future programs. Lead show‑stopper noise bugs during bring‑up and drive architecture‑level codesign trade‑offs across multiple dimensions. Qualifications BS / MS / PhD in EE, CE, or related discipline (or equivalent experience). 5+ years in silicon power integrity, voltage noise, or PDN. Deep expertise in one or more of: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, decap budgeting, voltage regulator response. Hands‑on silicon experience: bring‑up, characterization, and correlation. Comfortable on a bench with scopes, probes, DAQ, and simulators. Strong Sim‑to‑Si correlation instincts and system‑level objectivity. Ability to drive decisions through multiple collaborators without burning bridges. Spec rigor: sign‑off, document, and ship until requirements are met. Ways to Stand Out Patents or publications in power integrity, voltage noise, PDN, or di/dt mitigation. Experience with groundbreaking GPU, CPU, or AI accelerator silicon (Hopper, Blackwell, Rubin, or hyperscaler equivalents). Application of ML/AI to noise modeling, transient prediction, droop response, or feature optimization. Ownership of multi‑rail, multi‑domain PDN at SoC level – die + package + board co‑optimization in production. Track record of codifying methodology into reusable workflows or tooling. Compensation & Benefits Competitive base salary based on location and level (Level 3: USD 136,000 – 218,500; Level 4: USD 168,000 – 264,500) plus equity and benefits. Equal Opportunity Employer NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law. #J-18808-Ljbffr NVIDIA Corporation