Senior RTL Design Engineer

Design · San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX · Senior level A senior RTL design engineer typically owns block level design, integration, and sign off for complex SoC components. Strong candidates bring deep experience with Verilog or SystemVerilog, timing closure, and low power techniques, plus familiarity with on chip interconnect and memory interfaces. For a company building spatial processors and compilers for edge AI, the work centers on making hardware that runs AI models with very low power, so care with power, area, and correctness matters daily. How it fits the AI era AI changes this role by making power and efficiency the main constraints, since edge AI chips must run models without draining batteries or overheating. Tools can help with linting, test generation, and some optimization, but the hard parts remain human: choosing architectures, judging tradeoffs, and signing off that a design is correct and robust. The role stays hands on with silicon, where mistakes are costly and physical limits are real. How it builds AI experience This role builds AI experience by working on hardware that directly supports neural network workloads, especially the data movement and memory paths that dominate AI power use. A candidate can grow here by learning how model shapes and compiler choices affect RTL decisions, and by getting comfortable with power analysis for AI blocks. That combination of RTL skill and AI workload awareness is rare and valuable. Worth showing RTL design and integration Low power SoC techniques On chip interconnect Timing and power signoff This is our own read, written from the employer's posting and the company's Spotlight. The employer's posting is the source of truth for the role. About Efficient Computer Post-von-Neumann spatial processors and optimizing compilers for edge AI, which the company describes as ultra-low-power. #J-18808-Ljbffr present of AI