Principal SoC Design Engineer, HBM

Job ID: JR102410 Principal SoC Design Engineer, HBM As an SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet aggressive power, performance, area, and schedule targets. This is a hands‑on technical role focused on RTL design, IP integration, debug, and pre‑/post‑silicon support. Key Responsibilities Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. Support design verification through debug of simulation, emulation, and formal results; resolve functional, performance, and connectivity issues. Work closely with physical design teams to address synthesis, timing, power, and floorplanning considerations. Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues. Contribute to design documentation, block specifications, design reviews, and collaborate cross‑functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable designs; continuously improve design quality, reusability, and development efficiency through best practices and automation. Minimum Qualifications Strong experience in digital SoC design and RTL development. Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies. Experience with the RTL‑to‑GDS flow, including synthesis, static timing analysis, and design sign‑off considerations. Working knowledge of design verification concepts and debug workflows. Experience integrating complex IP blocks into large SoCs; familiarity with EDA tools from Cadence, Synopsys, and/or Siemens; programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting); ability to work effectively in a global, cross‑functional engineering environment; strong analytical and problem‑solving skills with attention to detail. Preferred Qualifications Experience with HBM, DRAM, or memory‑centric SoC designs. Familiarity with high‑speed interfaces, clocking strategies, reset architectures, and power management concepts. Exposure to DFT concepts (scan, MBIST, BIRA/BISR) and debug. Experience with hardware emulation or acceleration platforms (e.g., Palladium, Veloce, Zebu). Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field; minimum 10 years of experience in a related field; proven ability to mentor and develop junior engineers. Job Profile(s): Systems Design Engineer 5 Relocation Level: TBD Micron is a proud equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws. #J-18808-Ljbffr Micron Technology, Inc