SOC Integration Engineer
$120k - $275kMatX
What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here * Drive the evolution of MatX's silicon architecture-to-design methodology by engineering scalable solutions for the seamless integration of all Subsystems into a comprehensive full-chip SOC RTL design. * Partner with SubSystem owners within the Design team to facilitate block integration and spearhead the development of the System-On-Chip (SOC) Top-level
RTL.
* Implement advanced automation for SOC top-level RTL integration and build processes to enable on-the-fly generation of SOC top-level RTL. * Collaborate closely with the Full Chip owner on the Physical Design team to incorporate necessary RTL modules and feedthroughs/highways, ensuring alignment with chip-level floorplan connectivity requirements within the SOC RTL. * Establish robust clock and reset methodologies through cross-functional collaboration with system, architecture, design, and physical design teams. * Define and support SoC-level timing constraints, ensuring rigorous validation against Subsystem design and physical design requirements. * Provide technical support to package and board teams by defining SOC pin requirements and facilitating the generation of interposer netlists. Who You Are * Demonstrate proficiency in SystemVerilog and scripting languages such as Python or Perl to drive chip design RTL and associated flows. * Possess a proven track record in integrating high-performance computing elements (CPUs, GPUs, accelerators) and high-speed interconnect standards like UCIE, while managing memory and logical functionalities within the SOCRTL.
* Apply working knowledge of logical equivalency verification for SOC-level subsystem interfaces, collaborating with physical design teams to incorporate floorplan requirements into the RTL. * Manage memory wrapper generation, including the integration of DFT wrappers into Subsystem RTL. * Provide automation support for generating and configuring SOC RTL with user-defined Subsystems for Design Verification (DV) purposes. * Leverage hands-on experience with AI-driven tools to architect automation for SOC integration and facilitate technical support for cross-functional implementation teams. * Utilize hands-on experience with design synthesis, linting, clock & reset-domain-crossing, and timing constraint validation to ensure high-quality SOC sign-off. * Familiarity with emulation platforms and verification methodologies is highly desirable. Compensation The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.- Early Career - $120,000 - $275,000 + equity
- Mid Career - $175,000 - $450,000 + equity
- Senior Career - $275,000 - $600,000 + equity
- Team Connection Team Lunches, quarterly off-sites, and regular town halls
- Financial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even
- MatX E[x]tras $50 per month to use on the perks you care about most
- Remote Perks We work remotely Monday & Friday, supported by home-tech setup,
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