Design Verification Engineer

Insilico is an End-to-End specialized VLSI, Embedded Design & Software services and solutions company. It operates in the “Compute” & “Connectivity” space. Insilico is founded by industry veterans, who are strong leaders and practitioners with diverse experience in all the relevant aspects of technology and execution. The management and its entire team, handpicked from among the best talents in the industry, can adapt to the evolving technologies and growing market challenges internationally. Insilico has very flexible business models to suit a plethora of client needs. With a current clientele of top semiconductor companies, Insilico has a wide and diversified spectrum of service offerings in expansive domains within the ambit of Embedded Design & Software, and in almost all areas of VLSI design, from Spec-to-Silicon, on a wide range of ASICs & CPUs/GPUs in all the latest technologies, including 7nm. Being an integral part of a larger business eco-system, Insilico has the foundation of strong financials, validated processes, robust infrastructure and a global network of reputable clientele. Insilico’s service portfolio caters to products that empower the world of Communication, Networking, CPU/Servers, Automobile, Bio-Medicals, Consumer Electronics and a wide range of IOTs. Headquartered in the US, it has operations in India & APAC. Job Description Job Title: Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and verifying in any of the following key areas of our next generation ASIC: PCIE verification background 400G MAC verification background Additional Information All your information will be kept confidential according to EEO guidelines. #J-18808-Ljbffr Insilico