FPGA - Digital Engineer

Job ID: z5G7h3l6a1kMvyS65NP3c1XcxiaTkJ7Rj6FTXAKB3jU=Job Code: JPC 9036459Location: Rolling Meadows, IL, United StatesExperience: 5-15 yearsContact: RaghavendraContact Email: View email address on click.appcast.io Title: Digital Engineer 3 (2234)Location: Rolling Meadows, ILSecret Clearance: Active SecretPay Range: 90 – 95/hr. W2Must HaveDigital Signal Processing (DSP)PCB Design & LayoutXilinx FPGAXilinx VivadoJOB DESCRIPTIONOur Cinet Northrop Grumman Defense Systems is looking for a Sr. Principal Digital Design Engineer to join our team in Rolling Meadows, IL. As an integral member of the Special Tactical Electronic Warfare Systems (STEWS) team, selected Digital Design Engineer will participate in design, development, and modernization of systems that include airborne RF and IR systems, laboratory test stations, and transportable flight-line electronic combat system test sets.ResponsibilitiesDesigns, develops, modifies, and evaluates digital electronic parts, components or integrated circuitry for digital electronic equipment and other hardware systems. Determines design approaches and parameters. Analyzes equipment to establish operating data, conducts experimental tests, and evaluates results. Selects components and equipment based on analysis of specifications and reliability. May also review vendor capability to support product development.The Digital Design Engineer role involves full life-cycle product development from system concept and requirements through design, implementation, test verification, production, and field support. Digital subsystem and circuit card designs utilize the latest FPGA technologies from all major vendors and device families including Xilinx and Intel (Altera), and support high speed interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing, and processor interfaces. Your expertise in digital design and analysis, coding, verification, and synthesis using state of the art tools and techniques are desired for this position.Basic Qualifications for Engineer Digital 3Bachelor’s degree in electrical engineering, Computer Engineering, or similar engineering discipline with a minimum 9 years of digital electronics design experience or 7 years of digital electronics design experience with a master’s degree in a technical field.Extensive digital hardware circuit design experience, including simulation and schematic capture through test and integration.Ability to translate system performance and operational requirements into embedded system requirements, design, and test specificationsExperience in HDL (VHDL/Verilog)A thorough understanding of synthesis static timing closure, physical build (implementation) and image generation. Strong testbench generations and verification. Experience using Xilinx Vivado, Synopsys Synplify Pro and Mentor Graphics QuestaSim.Implementation of real time Digital Signal Processing algorithms within FPGAs. Experience with high-speed digital design techniques such as pipelining, asynchronous clock domains, synchronization, finite state machines, multi-cycling, and use of FIFOs.Familiarity with documentation and revision controlProven skills to include team leadership, mentoring others, communicating with all levels of an organization internally and externally, being adaptable, creative, collaborative, comfortable working independently, and enjoys solving difficult problems.Current Secret Security Clearance.Preferred Qualifications for Engineer Digital 3Advanced degree in Electrical or Computer Engineering with a minimum 12 years of digital electronics design experience.Algorithm modeling using MATLAB to generate bit-exact test vectors is desired Working knowledge of Electronic Warfare systems.Experience in Aerospace and/or Defense industries.Experience5-15 yearsSkills• Digital Signal Processing (DSP), • PCB Design & Layout, • Xilinx FPGA, • Xilinx Vivado, HDL (VHDL/Verilog), digital hardware circuit design experience, including simulation and schematic capture through test and integration, Digital Signal Processing algorithms within FPGAs.