Application Specific Integrated Circuit Verification Engineer

Job Description

ASIC UVM Verification Engineer

Role: Senior ASIC Verification Engineer Industry: Satellite Communications / Semiconductor Experience: 8+ years Key requirement: Strong hands-on SystemVerilog and UVM verification experience.

What the client is looking for

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• Multiple openings — candidates will be placed where their skills fit best.
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• Three verification levels: IP/Block-level, Subsystem-level, and SoC-level.
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• Well-rounded UVM engineers who can develop testbenches, debug complex designs, and drive verification to signoff.
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• Space experience is a plus.
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• DSP experience is a plus.
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Must-have technical skills

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• SystemVerilog and UVM.
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• ASIC/SoC functional verification.
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• Verification planning, assertions, and functional coverage closure.
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• Testbench development, scoreboards, reference models, and protocol monitors.
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• RTL and testbench debugging.
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• Complex digital control and datapath verification.
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Preferred experience

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• Satellite, wireless, modem, or baseband communications.
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• DSP pipelines, LDPC/BCH/FEC blocks, framing engines, or beamforming.
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• Formal verification, CDC/RDC, low-power verification, and high-speed interfaces.
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• Hardware/software integration and post-silicon debug.
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Ideal candidate profile

A senior UVM verification engineer with 8+ years of ASIC/SoC experience, strong SystemVerilog skills, and experience at one or more verification levels. Satellite or DSP expertise is beneficial but not mandatory.