Lead Software Engineer - C++, FPGA, Low Latency, Electronic Trading

Lead Software EngineerWe have an opportunity to impact your career and provide an adventure where you can push the limits of what's possible.As a Lead Software Engineer at JPMorgan Chase within the Electronic Trading Technology team, you are an integral part of an agile team that works to enhance, build, and deliver trusted market-leading technology products in a secure, stable, and scalable way. As a core technical contributor, you are responsible for conducting critical technology solutions across multiple technical areas within various business functions in support of the firm's business objectives.Job ResponsibilitiesExecutes creative software solutions, design, development, and technical troubleshooting with ability to think beyond routine or conventional approaches to build solutions or break down technical problemsDesign, develop, and test reliable, high-quality C++ code for trading connectivity and risk controls on Unix/Linux platforms. Implement end-to-end low latency client setups, including production rollout and post-release validation.Automate remediation for recurring issues to improve operational stability.Establish and execute test strategies for latency, throughput, and resiliency.Lead the development of market access trading and risk management modules.Participate across the software development lifecycle of electronic trading services.Collaborate with DevOps, Business Analysts, and Operations teams.Integrate FPGA pipelines with C++ software for deterministic performance.Drives team adoption of enterprise-authorized AI-assisted engineering practices within the work environment to improve code quality, delivery speed, and operational outcomes (e.g., AI-assisted code review/refactoring, test strategy acceleration, incident/root-cause analysis support), while establishing consistent validation standards (secure coding, peer review, automated testing) and promoting reuse of effective patterns across the team.Applies knowledge of tools within the Software Development Life Cycle toolchain, including enterprise-authorized AI-assisted development and automation capabilities, to improve the value realized by automation.Adds to team culture of diversity, opportunity, inclusion, and respectRequired Qualifications, Capabilities, and SkillsFormal training or certification on software engineering concepts and 5+ years applied experienceProficiency in modern C++ on Unix, Linux with strong multithreading and object-oriented design fundamentals. Ultra Low Latency experience requiredHands-on experience in system design, application development, testing, and operational stability in production environments.Scripting skills (Python, Perl, Shell) for automating development, testing, and operational tasks.Advanced understanding of Agile methodologies, including CI/CD, resiliency, and security. Ability to review and debug code written by others. Knowledge of low-level TCP/IP and network stack behavior.Comfort working closely with infrastructure and networking teams.Demonstrated experience leading effective use of approved AI-assisted software development tools (e.g., for coding, code review, test acceleration, troubleshooting) with the ability to set team expectations for validating AI outputs for correctness, performance, and security.Strong understanding of responsible AI use in engineering workflows, including data sensitivity considerations, secure handling of inputs/outputs, and adherence to resiliency and security expectations; experience coaching engineers on safe, compliant adoption within delivery practicesBachelor's degree in Computer Science, Engineering, Mathematics, or related discipline.In-depth knowledge of the financial services industry and their IT systemsPreferred Qualifications, Capabilities, and SkillsDemonstrated experience in low latency design and development using C/C++, including DMA, exchange connectivity, and pre-trade risk systems.Exposure to FPGA development for financial industry applications, including embedded software and kernel driver development for FPGAs and related systems.Proficiency in PCIe and low-latency networking (TCP/IP sockets, L1/L3 switching) in Linux, including FPGA-based hardware acceleration and Solarflare Ethernet NIC integration with C++.Experience implementing and certifying exchange connectivity using FIX, SBE, and native binary protocols, with a focus on low latency order entry, as well as creating and automating test strategies for functional and non-functional requirements in production-like environments.JPMorgan Chase & Co. is an Equal Opportunity Employer, including Disability/Veterans