Design Verification Technical Architect

What You Will Do

• Build State‑of‑Art Verification environment for IP, SS, SOC ranging from automotive to AI chips
• Lead verification team and execution of different projects to completion
• Hands‑on work in building verification environment involving processors, high speed peripherals (PCIe, UCIe, DDR)
• Work with cross‑functional (PD, DFT, Design, Emulation) team to resolve issues
• Responsible for DV deliverables and DV closure meeting required metrics such as code coverage, functional coverage

What You Will Bring

• 10+ YOE DV experience
• Good hands‑on knowledge of SV‑UVM
• Experience leading a team
• Experience building environment, verification plan, test plan
• Experience building reusable verification environment for SS, SOC
• Experience integrating third‑party VIP
• Python scripting expertise
• Use of source control such as git or equivalent
• Hands‑on experience with at least one high‑speed protocol (UCIe/PCIe5+/LPDDR5+/Ethernet200G+)
• GLS experience
• Arm Core/C‑Base experience
• Emulation experience and more
• Multiple high‑speed protocol experience

Pay Range

$150K to $190K

Benefits

Compensation decisions are based on experience, skills, education, and other job‑related factors. We offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.

Required Work Experience

• Verilog
• SV‑UVM
• Python
• Arm‑Core/RISC‑V
• C
• High‑speed protocols such as UCIe/PCIe5+/LPDDR5+/Ethernet200G+
• AMBA protocol
• Verification environment setup experience at SS/SOC level
• Planning and execution of entire project
• Integrating and using third‑party VIP
• Excellent communication skill and work in global environment