Sr. Principal Software Engineer (Austin)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Cadence Design Systems is looking for a highly motivated hardware engineer to work with the Modus R&D engineering team in the Design-For-Test (DFT) IP business unit.As a member of the DFT R&D team, you will design and implement advanced Design‑for‑Test (DFT) hardware, test fabrics, and on‑chip test networks used in next‑generation SoCs. You will contribute to the hardware and software development of industry‑leading test solutions such as scan compression, hierarchical test access architectures, Logic Built-In-Self-Test (LBIST), Memory Built-In-Self-Test (MBIST) , Power-On-Self-Test (POST), and In-System Test (IST). Your work will directly support high‑coverage, low‑cost test strategies across complex semiconductor designs.Required SkillsRTL Design & VerificationStrong background in Verilog/SystemVerilog RTL for digital hardware design and simulationHands-on coding and automation skills using SystemVerilog/Verilog, plus scripting with Perl and PythonMastery of UVM and directed testbench IP verification, including test planning, coverage closure, debug, and working with verification teams to drive qualityKnowledge of network structures and method for communicating data across an SoCFull-Flow Development & IntegrationProven experience developing complex reusable IPs from architecture through deliveryStrong experience with synthesis, lint, CDC/RDC, formal checks, timing closure, physical design, and signoff workflowsAbility to manage internal and third-party/services IP integrations, including requirements review, interface alignment, quality checks, and delivery trackingAbility to debug complex hardware issues across RTL, verification, synthesis, timing, and integration environmentsStrong documentation skills for architecture specs, design specs, integration guides, and verification collateralDFT ArchitectureDeep understanding of digital design architecture, including subsystem integration, DFT, interconnects, memory-mapped interfaces, reset/clock architecture, and low-power design considerationsStrong knowledge of DFT requirements for SoCs, including scan, MBIST, LBIST, POST, IST, IJTAG, test access architecture, and design-for-testability tradeoffsKnowledge of DFT IP concepts, hardware, and test network communicationProject Ownership & Team CommunicationExperience leading design reviews, architecture reviews, microarchitecture reviews, and implementation readiness reviewsStrong project execution and project management skills, including planning, dependency tracking, risk management, milestone ownership, and cross-functional coordinationAbility to mentor senior and junior engineers and provide technical leadership across teamsGood communication skills with a development team spread across multiple locationsPrior experience with large software development projects is highly recommendedPreferred SkillsExperience with ISO 26262 functional safety concepts, including safety mechanisms, diagnostic coverage, safety requirements, and ASIL-oriented design flowsExposure to security-aware hardware design, including secure boot concepts, access control, lifecycle management, key handling, or secure debugExperience with automotive, industrial, AI, or hyperscaler-class IP developmentFamiliarity with Cadence flows such as Xcelium, JasperGold, Genus, Innovus, Tempus, Modus, and related signoff/debug environmentsExperience driving IP maturity through reusable methodology, quality metrics, and scalable infrastructureThe annual salary range for California is $196,000 to $364,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.We’re doing work that matters. Help us solve what others can’t.SummaryLocation: AUSTINType: Full time