Staff/Sr. Staff GPU Engineer - Shader System RTL Design/Microarchitecture

Category Chip Design Location San Diego, CA Experience More than 4 Years Work Expe. Job Description About the Team: With MediaTek’s leadership in SoC design, the MediaTek GPU IP team is committed to developing industry‑leading, feature‑rich, and highly PPA‑competitive graphics IP. Our GPU technology is deployed across flagship and mainstream mobile SoCs and is also a foundational technology for adjacent markets including laptops, IoT, AI, VR/AR, automotive, and custom ASIC applications. The team is expanding and hiring top GPU talent across multiple disciplines, including architecture, microarchitecture, RTL design, software drivers, compiler technology, performance modeling, power optimization, and silicon validation. Positions are available in our San Diego and San Jose offices. Position Overview: We are seeking a Staff / Senior Staff GPU Engineer specializing in Shader System RTL Design and Microarchitecture to help define, design, and deliver next‑generation GPU IP. The ideal candidate will have strong hands‑on experience in GPU shader subsystem microarchitecture, RTL implementation, performance analysis, functional debug, and PPA optimization. In this role, you will drive the design and optimization of GPU shader systems, including shader core pipelines, thread/warp/wave scheduling, instruction dispatch and issue, execution pipelines, register files, operand collection, scoreboard and dependency management, load/store interaction, cache/memory interfaces, synchronization, and cluster‑level integration. You will collaborate closely with architecture, compiler, software driver, performance modeling, verification, physical design, and post‑silicon teams to deliver best‑in‑class GPU IP for mobile, automotive, laptop, IoT, AI, VR/AR, and ASIC markets. Role and Responsibilities Define, develop, and own GPU shader system microarchitecture specifications for industry‑leading graphics and compute IP. Lead RTL design and microarchitecture development for shader‑related blocks, including shader core pipelines, thread dispatch, warp/wavefront scheduling, instruction issue, operand collection, register file access, scoreboard, dependency tracking, execution control, and pipeline flow control. Design and optimize GPU execution resources, including SIMD/SIMT pipelines, scalar/vector execution units, special function units, load/store interfaces, synchronization mechanisms, barrier handling, and shader control logic. Drive shader subsystem integration with GPU front‑end, geometry/tiler, raster, texture, cache, memory subsystem, command processor, firmware, and render backend blocks. Collaborate with GPU architecture and compiler teams to translate ISA behavior, API requirements, shader workload characteristics, and performance targets into efficient hardware specifications. Work closely with RTL, verification, performance modeling, physical design, software driver, compiler, and post‑silicon teams to identify and resolve architectural, microarchitectural, implementation, timing, and power bottlenecks. Analyze GPU workloads and performance data to optimize shader occupancy, instruction throughput, latency hiding, register pressure, cache locality, memory bandwidth efficiency, workload balancing, and power efficiency. Drive PPA optimization across shader subsystem design, balancing power, performance, area, timing, frequency, utilization, and implementation complexity. Contribute to full GPU IP development lifecycle, including microarchitecture definition, RTL coding, lint/CDC/RDC cleanup, functional verification support, synthesis, timing closure, tape‑out, bring‑up, and post‑silicon debug. Debug and resolve complex pre‑silicon and post‑silicon issues related to shader functionality, performance, power, timing, and area. Develop and review high‑quality SystemVerilog RTL and microarchitecture documentation with strong emphasis on correctness, scalability, reuse, and maintainability. Partner with verification teams to define test plans, coverage goals, assertions, debug strategies, and directed/random test scenarios for shader subsystem validation. Influence future GPU architecture directions through technical analysis, shader workload studies, performance modeling, competitive benchmarking, and PPA exploration. Apply AI‑assisted tools and automation to improve productivity in RTL development, functional debug, performance analysis, regression triage, and PPA optimization. Deliver high‑quality technical results while meeting project milestones, schedules, and product requirements. Build trusted and effective working relationships across internal teams, external partners, and cross‑site engineering organizations. Contribute to best‑in‑class GPU IP for mobile, automotive, laptop, IoT, AI, VR/AR, and ASIC applications. Main Requirements and Qualifications Minimum Qualifications BS, MS, or PhD degree in Computer Science, Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience. 8+ years of experience for Staff level, or 10+ years of experience for Senior Staff level, in RTL design, microarchitecture, or architecture for complex GPU, graphics, processor, AI accelerator, DSP, or high‑performance SoC subsystems. Strong hands‑on experience with SystemVerilog, Verilog, VHDL, C/C++, and scripting languages such as Python, Perl, Tcl, or shell scripting. Proven experience designing or implementing complex RTL blocks with strong understanding of timing, area, power, clocking, reset, CDC/RDC, low‑power design, and synthesis constraints. Solid understanding of computer architecture, GPU architecture, processor pipelines, parallel execution models, memory hierarchy, interconnects, and performance/power trade‑offs. Experience defining or implementing microarchitecture specifications for complex hardware blocks or subsystems. Experience with RTL design quality flows, including lint, CDC, reset analysis, synthesis, formal checks, assertions, waveform debug, and regression debug. Experience with performance analysis, bottleneck identification, power optimization, area optimization, and hardware design trade‑off analysis. Strong debugging and root‑cause analysis skills across simulation, emulation, FPGA, and/or silicon environments. Ability to work effectively with architecture, verification, physical design, software, compiler, performance, and post‑silicon teams. Excellent verbal and written communication skills. Strong technical leadership capability, self‑motivation, ownership mindset, and ability to drive complex tasks independently. Ability to thrive in a dynamic, fast‑paced, and technically challenging engineering environment. Preferred Qualifications Deep knowledge of GPU shader architectures, including SIMT/SIMD execution, warp/wavefront scheduling, thread dispatch, instruction issue, scoreboarding, register files, operand collection, execution pipelines, and latency hiding. Hands‑on experience with GPU shader core or shader subsystem microarchitecture, including: Instruction fetch, decode, dispatch, issue, and retirement Scoreboard and dependency tracking Register file design and banking optimization Operand collection and bypass networks ALU, FPU, SFU, tensor, or matrix execution integration Load/store unit and memory coalescing Texture, cache, and memory subsystem interaction Barrier, synchronization, atomic, and memory ordering logic Context switching, preemption, virtualization, or security support Performance counters, debug hooks, and hardware profiling support Clock gating, power gating, DVFS, and low‑power shader design Experience with modern GPU graphics and compute workloads, including vertex, pixel/fragment, compute, mesh, geometry, tessellation, ray tracing, or AI/ML shader workloads. Knowledge of GPU ISA design, shader compiler interaction, instruction scheduling, register allocation, occupancy, and compiler‑hardware co‑optimization. Familiarity with modern graphics and compute APIs such as Vulkan, Direct3D, OpenGL/OpenGL ES, Metal, OpenCL, or related programming models. Experience with tile‑based rendering, immediate‑mode rendering, unified shader architectures, or mobile GPU design. Experience with GPU performance modeling, architectural simulation, trace analysis, workload characterization, graphics benchmark analysis, or hardware performance counter analysis. Familiarity with mobile GPU design constraints, including power efficiency, thermal limits, memory bandwidth optimization, area constraints, and SoC‑level integration. Experience collaborating with software driver, compiler, performance, verification, and physical design teams to optimize shader system performance and implementation quality. Experience with pre‑silicon validation, emulation, FPGA prototyping, post‑silicon bring‑up, silicon debug, performance counter analysis, or hardware profiling tools. Familiarity with advanced process nodes and practical physical design considerations, including timing closure, congestion, placement‑aware RTL design, multi‑clock design, and low‑power implementation. Familiarity with AI‑assisted engineering workflows, automation frameworks, or productivity tools for RTL coding, verification, debug, regression triage, and performance/PPA exploration. Salary range: $150,000- $244,000 Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual’s skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, company paid holidays, sick leave, vacation time, parental leave, 401(k) and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. #J-18808-Ljbffr MediaTek Research Lab Inc.