Member of Technical Staff, ASIC Verification

About the Role We are seeking a Member of Technical Staff, Senior ASIC Verification Engineers. This role demands proven technical leadership in ASIC verification and simulation methodologies. You will propose and setup the optimum verification methodology. You will be part of an early‑stage startup working on an exciting product in the Artificial Intelligence/DataCenter space. The work involves learning advanced LLM in modern data centers and applications to design memory acceleration. This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA. Essential Duties & Responsibilities As part of the Verification team, you will be responsible for verification of Netpreme silicon, IP and subsystems. Provide technical leadership in defining IP/SOC verification from microarchitecture to design to tapeout. Conduct design reviews to ensure adherence to best practices. Guide the team in optimizing the design to meet aggressive performance, power and area goals. Drive effective and seamless collaboration with partner teams across architecture, design, physical design, firmware, DFT, and post silicon domains to ensure successful system level functionality. Interface with external IP vendors, foundries and EDA tool providers to ensure dependencies and roadblocks are addressed in a timely fashion to support team deliverables. Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Minimum of 5+ years of ASIC/SOC verification. Excellent leadership, communication and stakeholder management skills. Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints. Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape‑out in advanced process technologies. Outstanding technical expertise in verification methodologies. Hands‑on design experience in one or more industry standards/protocol stacks such as Ethernet, UCIe, UALink etc. Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory). Proficiency with front‑end development tools/methodologies, and scripting for automation and flow integration. Verification and tapeout of any advanced silicon device is highly preferred. Post‑Silicon validation of any silicon ASIC/SoC is highly preferred Preferred Qualifications PhD in Electrical Engineering, Computer Engineering, or a related field. Experience managing relationships with external design partners, IP vendors, and foundries. Knowledge of Design‑For‑Testability, post silicon debug/validation/manufacturing test. Compensation & Benefits Competitive salary commensurate with experience including base salary, performance‑based bonus, and early stage equity grant Comprehensive benefits including health, dental, vision, and life insurance Well‑equipped, sunny offices in Santa Clara, CA and Boston, MA Relocation assistance and visa sponsorship Perks include a daily lunch stipend, 401k match, and more A collaborative, continuous‑learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high‑performance computing The Opportunity Impact: We are tackling a fundamental challenge at the infrastructure layer: unlocking greater AI capability while dramatically improving efficiency. The work we do here compounds across state‑of‑the‑art AI models, systems, and real‑world applications. Timing: Joining now means real ownership of the company and meaningful influence over product direction and execution. You’ll work from first principles, move quickly from insight to execution, and see your contributions directly reflected in what we build. Culture: You’ll work alongside a group of people who care deeply about rigor, clarity, and impact. We value thoughtful disagreement, fast learning, and intellectual fearlessness. This is a place where strong ideas shine, curiosity is encouraged, and growth is a daily practice. #J-18808-Ljbffr