DFT Lead - 2.5D/3D Test Architect (Bay Area)
Eximietas Design
Eximietas Design is seeking a DFT Lead to oversee test architecture and silicon implementation for advanced packaging projects. This role requires 10–15 years of hands-on DFT experience, including expertise in ATPG methods using tools like Synopsys TetraMAX. You'll work closely across teams and have a major impact on production silicon programs. The position is primarily onsite in the Bay Area with hybrid flexibility. Your leadership will ensure the DFT direction for next-generation projects, and you'll mentor team members to elevate engineering capabilities. #J-18808-Ljbffr
- ...Type: Full-time Location: Bay Area, California — primarily onsite... ...is hiring a seasoned DFT (Design for Test) Lead to drive test architecture... ...implementation for next-generation 2.5D / 3D designs. This is a hands‑... ..., and compression. Architect and integrate scan, MBIST,...3DPermanent employmentFull timeContract workImmediate start
- Nvidia Corporation is seeking a DFT Engineering professional to innovate and implement sophisticated designs for test access mechanisms on complex semiconductor chips. The successful candidate will collaborate with cross-functional teams, develop methodologies for next-...Suggested
$171k - $272k
...MediaTek is seeking a technical leader with expertise in Packaging Architecture, specifically in 2.5D/3D/3.5D technologies. This role requires collaboration across various teams to develop innovative packaging solutions for automotive, datacenter/HPC, and computing applications...3D- Hewlett Packard Enterprise Development LP in Sunnyvale, CA is looking for a seasoned engineer to develop test strategies and DFT solutions for ASICs and 2.5D SiPs. The ideal candidate will have over 15 years of experience, focusing on innovative designs with strong collaboration...Suggested
$175k - $350k
...Role As the HSIO Architect, you will own the... ...Engineering, digital leads, and analog teams. You... ...error handling • Drive DFT and compliance test architecture for PCIe... ...-die integration in 2.5D/3D packages • Signal... ...Team • US team: Bay Area preferred, but we hire...3DRemote workShift work- ...Synopsys, Inc. is seeking an Architect in Applications Engineering to lead product validation and deployment. This... ...will enhance usability of Synopsys Test products, contribute to customer integrations... ...15 years of relevant experience in DFT for SoC/ASIC development. Strong...
$216k - $345k
...Principal Solutions Architect – Semiconductor... ...Architect to define and lead the technical... ...for semiconductor test. This covers wafer... ...test engineering for DFT architecture decisions... ...three of the following areas: ATE platform... ...packaging test challenges (2.5D/3D, chiplets, KGD).*...3D$220.2k - $330.4k
...Technologies, Inc. Job Area: Engineering Group,... ...Position: Signal Integrity Architect We are seeking an... ...component suppliers. You will lead the definition,... ...Perform early SI analysis on 2.5D/3D structures and establish... ...and compliance testing using tools like VNAs,...3DWork experience placementWork from home- * Responsible for developing test strategy and DFT (Design-for-Test) solutions for ASICs and 2.5D SiP (System-in-Package) that supports... ...in testability and DFT area for ASICs, memories, and 2.5D SiPs... ...Bandwidth Memory) DRAM, 2.5D, and 3D ICs* Broad experiences with ASIC...3DContract workLocal area
- ...Principal ASIC Test Development Engineer This role... ...you will work on average 2 days per week from an HPE... ...developing test strategy and DFT (Design-for-Test)... ...experience in testability and DFT area for ASICs, memories, and... ...Memory) DRAM, 2.5D, and 3D ICs Broad experiences...3DContract workWork experience placementWork at office2 days per week
$162k - $218k
Lead Product Designer - Matterport - SF Bay Area CoStar Group (NASDAQ: CSGP) is a leading global provider of commercial and residential real estate information... ...we maintain a drug-free workplace and perform pre-employment substance abuse testing #J-18808-Ljbffr CoStar GroupFull timeWork at officeRemote workFlexible hours$196k - $368k
NVIDIA is seeking a Lead ATE Test Development Engineer for their LPU team in Santa Clara, CA. You will define, develop, and implement ATE test development processes to support high-quality product transfer to mass production. We are looking for candidates with 12+ years...$180k - $220k
...Values Be Fearless : Unmute yourself. Test boundaries and get proven right.... ...an experienced and highly motivated Lead Vector Compute Architect to lead the architecture definition and... ...requires someone to be local to the Bay Area. What you'll do Drive architecture tradeoff...Local area$129.34k - $161.09k
...The Lead Account Manager for Thermal & Assembly Solutions... ...packaging solutions 2. 3-in-a-Box Leadership &... ...opportunities (N+1, N+2) Expansion areas in AI/datacenter... ...Advanced packaging (2.5D/3D, chiplets, HBM) Thermal... ..., Pacific Northwest, or Bay Area proximity optional...3DPermanent employmentFull timeContract workTemporary workWork experience placementWorldwideRelocation packageFlexible hours- ...team is looking for a passionate and experienced DFT/DFx Methodology, Architecture, and RTL Execution Lead to support high-speed SerDes PHYs , next-generation... ...methodology development, scan integration support, test constraints, ATPG support, and post-silicon debug...
$205k - $285k
Google Inc. is seeking a Food Program Manager for the Bay Area to lead the strategic execution of the Food program across headquarters. You will ensure high-quality services while managing vendor partnerships and utilizing data-driven insights. With a focus on operational...Full time- ...experience in SoC DFT architecture and design... ...employees and leading multiple SoC... ...with a focus on VLSI testing, fault tolerance,... ...nodes (5nm/3nm), 2.5D/3D‑IC packaging, or high... ...count, and silicon area overhead. Collaborate... ...Design and Power Architects. Support the post...3DWorldwide
- ...Bolt Graphics, Inc. is seeking a Lead SoC Architect to define the technical direction for next-generation semiconductor products in Sunnyvale... ...AI and GPU systems. Applicants should be local to the Bay Area and eager to lead while being an individual contributor. #J-...Local area
$175k - $350k
...We are seeking a SoC Architect to define and drive the architecture of next‑generation XPUs... ...Drive trade‑offs across performance, power, area, and cost. Define system‑level... ...chiplet architectures and advanced packaging (2.5D/3D). Knowledge of coherency protocols (CXL,...3D$136.5k - $253.5k
...Lead Red Hat Linux Architect At Cadence, we hire and develop leaders and innovators... ...cloud infrastructures. 2. Cloud Operations Management... .... Technical Focus Areas Monitoring & Observability... ...Lifecycle Management Plan and test RHOSP upgrades in lab/...- ...week Hybrid. The role: Principal Architect- Performance Analysis and... ...technologies (such as DIMC, D2D, 3D-DRAM etc.) and emerging workloads... ..., performance implications (2) Creating analytical models to... ...experience in multiple of the relevant areas - computer architecture,...3D3 days per week
- ...semiconductor products. This role focuses on 2.5D and 3D heterogeneous integration , enabling... ...semiconductor industry. Key Responsibilities Lead the design and development of 2.5D/3D... ...cost optimization Support DFx (DFM, DFT, DFA) and reliability validation (warpage...3DFull time
- NVIDIA Gruppe is looking for a senior test development engineer in Santa Clara, California. This role involves driving quality and automation for AI microservices, leading testing strategies, and providing mentorship to engineers. The ideal candidate will have 8+ years...
- Google Inc. is seeking an expert in SoC DFT architecture. You will shape the future of AI/ML hardware acceleration by driving innovative TPU technology. Your role involves leading extensive DFT processes for multiple SoCs, ensuring top-tier product quality from design through...
- ...Assembly Design Kit) Development Engineer to lead the creation, integration, and validation of design enablement infrastructure for 2.5D/3D advanced packaging , including chiplet-... ...design creation ~ Automated regression testing ~ Cross-tool consistency checks ~...3DFull time
$152.5k - $244k
...Advanced Defect Modeling And Testing (Technical Manager)... ...semiconductor processes and 3D packaging technologies.... ...and yield of advanced 2.5D/3D packaging... ...patents and publications in leading conferences and journals... ...verification tools, and DFT/ATPG methodologies for packaging...3DVisa sponsorship$198k - $297k
...powered products. We deliver industry-leading silicon design, IP, test, simulation and analysis solutions.... ...the ingenuity of tomorrow. As an Architect in Applications Engineering, this role... ...Facilitating successful integration of DFT-IP into customer designs,...- ...Customer Package Design Integration Engineer (2.5D / 3D Packaging) to ensure the successful... ...Customer Design Integration & Enablement Lead customer design bring-up using Rapidus... ...debugging and issue resolution in areas such as: SI/PI and signal integrity challenges...3DFull time
- ...Lead Test Analyst - Usability Tester – Manual Tester Client: California Department of Corrections and Rehabilitation (CDCR) Location... ...execute the testing effort of large complex State IT projects. 2. Demonstrated experience mentoring SMEs and Usability Testers...For contractors
$150k - $230k
...areseekingan experienced process lead engineer in the field of... ...thermal modelling. Support device testing automation and data analysis... ...projects. Provide DFM, DFR, and DFT inputs for HQ RnD teams for... ...0,000 - 230,000 USD per year (Bay Area, CA) #J-18808-Ljbffr Lyte AI...Contract workWork experience placementWorldwideFlexible hours
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