RTL Design Manager (San Jose)

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As an RTL Design Manager for the AECG IP & SOC group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.THE PERSON:A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.KEY RESPONSIBLITIES:Lead a small, high-performance engineering teamOwn the design and implementation of blocks to meet functional, timing, area and power requirements Guide and review verification for these blocksDesign and implement logic functions that enable efficient test and debugImplement automation to increase design team efficiencyStrong front-end RTL engineering backgroundStrong communication skills, able to summarize complex problems for executives as well as drill down to details with architects and engineersStrong analytic and problem solving skills including the ability to analyze current behavior, identify potential areas for improvement, and design of experimentPREFERRED EXPERIENCE:Experience with Arm architecture and APB, AXI, CHI protocolsExperience with design reuse, including RTL, constraints, and waiversExperience with SoC level design integrationExperience with automation using scripting techniques such as PERL, Python, or TclExperience with timing constraints and timing exceptionsExperience running standard quality checks such as LINT and CDCExperience designing with multiple power domains including writing UPFMust be a self-starter and self-motivatedACADEMIC CREDENTIALS:Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION:San Jose, CAThis role is not eligible for visa sponsorship.#LI-SL2#LI-HYBRIDBenefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.