Silicon Design Verification Engineer

Microsoft Silicon Cloud Hardware and Infrastructure Engineering (SCHIE) is the team behind Microsofts expanding Cloud Infrastructure and responsible for powering Microsofts Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsofts over 200 online businesses including Bing MSN Office 365 Xbox Live Teams OneDrive and the Microsoft Azure platform globally with our server and data center infrastructure security and compliance operations globalization and manageability solutions. Our focus is on smart growth high efficiency and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design development manufacturing and packaging of Microsofts state-of-the-art computer chips notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.

As Microsofts cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time in high volume with high quality and lowest cost is of paramount importance. To achieve this goal the Shared and Custom IP & Silicon (SCIPS) team is instrumental in defining and delivering operational measures of success for hardware manufacturing improving the planning process quality delivery scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for Silicon Design Verification Engineer to join the team.

#SCHIE #CSME #SCIPS

• Develop C and C based test content low-level drivers and custom firmware at the subsystem and SoC levels including self-checking tests that run on embedded processors.
• Extend the compile and build flow to support custom firmware-style tests.
• Serve as a technical owner for the teams FPGA prototyping platforms (such as HAPS or Xilinx): create board images and bit files. Design additional custom FPGA RTL for protocol interfaces and feature enablement. Release stable platforms to the firmware team and keep them working as the design evolves.
• Develop and extend custom python tooling to interface with the FPGA platform.
• Debug FPGA and post-silicon issues using tools such as JTAG debuggers logic analyzers oscilloscopes and multimeters
• Drive post-silicon bring-up and validation in the lab: run the validation suites on first silicon meet bring-up exit criteria on schedule and debug platform issues such as JTAG failures UART connectivity and boot failures alongside the design firmware hardware and security teams.
• Root-cause failing post-silicon tests to closure collecting and analyzing scan dumps for low-level issues such as boot ROM and built-in self-test bugs coordinating cross-team debug and delivering fixes such as handling fatal errors correcting driver access violations and reconciling registers modified by boot firmware.

Required/minimum qualifications

• Masters Degree in Electrical Engineering Computer Engineering Computer Science or related field AND 1 year(s) technical engineering experience OR Bachelors Degree in Electrical Engineering Computer Engineering Computer Science or related field AND 2 years technical engineering experience OR equivalent experience.

Other Requirements

• Ability to meet Microsoft customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations the EU Dual Use Regulation and/or other export control a condition of employment the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g. under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement and as a condition of employment the successful candidates citizenship will be verified with a valid passport. Lawful permanent residents refugees and asylees may verify status using other documents where applicable.

Preferred Qualifications:

• Experience developing C and C test content for subsystem and SoC verification including bare-metal and firmware-style tests with working knowledge of SystemVerilog testbenches.

• Experience bringing up and maintaining FPGA prototyping or emulation platforms (such as HAPS or Xilinx) including board images platform tooling and testbench changes that enable firmware and validation teams.
• Hands-on hardware debug experience with tools such as JTAG debuggers logic analyzers oscilloscopes and multimeters
• Experience owning pre-silicon verification of IP subsystems or SoCs through the full cycle including test planning test development failure debug and coverage signoff.
• Experience with post-silicon bring-up and validation including running test suites on silicon and debugging boot platform and connectivity issues in a lab environment.
• Proficiency in Python or a similar scripting language such as Perl or Ruby for test automation build flows and log or data parsing.
• In-depth knowledge of verification principles testbench architecture and stimulus generation with a track record of debugging complex designs.
• Experience with low-level and embedded software including assembly startup code linker scripts and Makefile-based build flows.
• Familiarity with industry protocols such as AMBA (AXI/AHB/APB) JTAG SPI I2C/I3C and USB.
• Experience collaborating across architecture design firmware and validation teams with strong communication skills.
• Understanding of silicon and/or computer architecture.

Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102100 - $202200 per year. There is a different range applicable to specific work locations within the San Francisco Bay area and New York City metropolitan area and the base pay range for this role in those locations is USD $133800 - $219200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
position will be open for a minimum of 5 days with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age ancestry citizenship color family or medical care leave gender identity or expression genetic information immigration status marital status medical condition national origin physical or mental disability political affiliation protected veteran or military status race ethnicity religion sex (including pregnancy) sexual orientation or any other characteristic protected by applicable local laws regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process read more about requesting accommodations.

Required Experience:

IC