Intermediate Semiconductor Process Engineer

Intermediate Semiconductor Process Engineer (BH-396976) Location: Santa Clara, United States. Salary: $45 to $53 per hour. 12‑month contract to hire. The Big Picture – Top Skills You Should Possess: Solid interpersonal skills Strong analytical skills Ability to quickly adapt to change What You Will Be Doing: Design, collect data, analyze, and compile reports on process engineering experiments for defect reduction within safety guidelines. Troubleshoot defect problems, perform Root Cause Analysis, and resolve moderately difficult process engineering issues. Implement new technology, products, and analytical instrumentation to support defect studies. Design the failure analysis (FA) DOE for key defect-critical components to troubleshoot wafer defect issues on R&D programs and major customer escalations. Perform the FA, collect and analyze data within safety guidelines. Communicate FA observations and recommend solution paths in defect troubleshooting. Measure wafer defect/film properties and organize data/reports to support defectivity improvement by SEM/FIB. Prepare wafers for experimentation, including cleaning, loading, and preparation of klarf files. Operate scanning electron microscope (SEM) for top‑view or critical dimension and energy dispersive spectroscopy (EDS) analysis, identifying patterns of interest and optimizing conditions. Prepare samples for Focused Ion Beam (FIB) lamella making using Zeta Marking tool, optimizing sample preparation and identifying cutting locations. Operate and check performance of equipment for sample prep under limited supervision. Understand SEM and FIB principles. Perform SEM/FIB system software alignment functions and routine maintenance (flash, plasma clean, etc.). Perform routine shutdown procedures, identify problems, and call for service when necessary. Coordinate instrument repair and maintenance; coordinate with engineering on wafer evaluations. Order equipment and supplies and coordinate with vendors and purchasing. Report and communicate wafer defect analysis results, recommending solution paths for wafer defect troubleshooting on key R&D programs. Interact with vendors/suppliers to evaluate and troubleshoot the latest defect metrology tools (SEM, EDX, FIB, Wafer scribing). Develop and publish best‑known‑method (BKM) procedures including sample prep, SEM conditions, and special sample handling. Generate internal documentation for products, presentations, and technical reports. What You Need to Bring to the Table: Provide training for junior engineers on wafer preparation/analysis with defect metrology tools. Contribute to and manage the Metrology tool (Zeta/SEMVision) operation. Interface with requesters, understand detailed requirements, and communicate results. Help the lab monitor wafer in process (WIP) and maintain quality, turnaround time, and throughput. Define and forecast the defect metrology tool requirements to support N+ defect requirements. Bonus Points! Otherwise Known As Preferred Qualifications: Experience in semiconductor industry: 1‑2 years. Minimum two years of college: Associate's Degree. Benefits Medical, Dental & Vision Benefits 401K Retirement Savings Plan Life & Disability Insurance Direct Deposit & weekly e‑payroll Employee Discount Programs Referral Bonus Programs Certification and training opportunities Health Savings Account (HSA) (for employees working 20+ hours per week) MetLife Voluntary Benefits Employee Assistance Program (EAP) Equal Opportunity Employer Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. #J-18808-Ljbffr Yoh,-A-Day-