PCIe RTL Design Engineer for TPU Accelerators
Google Inc.
A leading tech company based in Sunnyvale, CA is seeking a PCIe Design Engineer to lead the design of high-performance ASICs for AI/ML hardware acceleration. The role involves RTL development, managing comprehensive documentation, and integrating subsystem functionality within data center accelerators. Candidates should hold a Bachelor's degree and possess significant experience in ASIC design, specifically with PCIe logic. The position includes a competitive salary range and opportunities for growth within a collaborative environment. #J-18808-Ljbffr Google Inc.
Vacancy posted 4 days ago
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