Principal Design Verification Engineer - PCIe / High-Speed SoC

Job Title: Principal Design Verification Engineer - PCIe / High-Speed SoCLocation: Santa Clara, CACompensation: $200K - $250K base DOE plus bonus and RSUs ($300K - $350K+ total comp.)Requirements: Design Verification, High-Speed SoC, PCIe / UALink / SerDes, SystemVerilog, UVMPosition OverviewWe are seeking a Principal Design Verification Engineer with deep expertise in PCIe and high-speed SoC verification to lead verification efforts for next-generation multi-core SoCs. This role will own verification planning, architecture, and execution for complex IP (PCIe, SerDes, UALink, interconnect) and full-chip integrations, drive closure of functional coverage and sign-off criteria, and mentor a team of verification engineers. The ideal candidate combines strong hands-on technical skills (SystemVerilog/UVM, Python, C++, scripting) with proven leadership in large-scale SoC verification projects and experience with EDA verification tool flows.Key ResponsibilitiesDefine and drive verification strategy and plans for PCIe IP, SerDes subsystems, and high-speed SoC integrations to achieve tape-out quality sign-off.Lead development of modular, reusable UVM/ SystemVerilog verification environments and testbenches for IP and subsystem-level verification; ensure portability and maintainability.Create and maintain directed and constrained-random test suites, protocol-aware tests for PCIe root/endpoint behavior, error handling, and power/clock domain interactions.Develop and maintain functional coverage models and closure plans; analyze coverage holes and direct debugging and rework to meet coverage targets.Architect and implement bring-up and silicon validation support, including creation of bring-up tests, debug scripts, and root-cause analysis for silicon failures.Drive cross-functional collaboration with architects, RTL designers, firmware/driver teams (ARM), and physical design to resolve verification issues and ensure correct integration.Leverage and extend EDA verification tool flows (simulation, emulation/FPGA prototypes, static checks, formal) and manage regression infrastructure for large-scale verification runs.Develop and maintain verification automation (Python, Perl, shell), including test orchestration, result parsing, and metrics dashboards.Mentor and lead verification engineers, perform code/review sessions, set best practices for assertions, UVM factories, scoreboards, and reuse methodologies.Evaluate and integrate third-party verification IP and tools (e.g., protocol analyzers, link-layer tools such as UALink) to accelerate verification and validation.Contribute to performance and power verification scenarios, multi-core coherency testing, and system-level scenarios involving DMA, interrupts, and memory subsystems.QualificationsBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field; PhD a plus.10+ years of experience in design verification with a strong focus on SoC and high-speed interfaces (PCIe, UALink, Ethernet, SerDes etc.); proven track record leading verification for complex silicon projects.Deep knowledge of PCIe protocol (link training, LTSSM, transaction/completion semantics) and hands-on experience verifying PCIe IP (root/endpoint/Switch).Extensive experience with SystemVerilog and UVM for verification environment development and testbench architecture.Strong scripting and automation skills (Python required; Perl and shell scripting desirable) and proficiency in C++ for verification components or tools.Hands-on experience with EDA verification tools (simulation like Synopsys VCS/Questa/Incisive, emulation, formal tools, coverage analysis tools) and large regression/CI workflows.Experience with SerDes, PHY-level behaviors (link equalization, PAM-n, BER testing), and high-speed link characterization.Familiarity with ARM-based firmware/bring-up flows and validating multi-core SoC interactions (interconnects, coherency, cache behavior).Proven expertise in functional coverage-driven verification, assertion-based verification (SVA/PSL), and coverage closure methodologies.Experience with third-party tools and link analyzers such as UALink or similar protocol tools is a plus.Strong problem-solving, debugging and root-cause analysis skills; able to drive issues to closure in fast-paced environments.Excellent communication and leadership skills with experience mentoring engineers and coordinating cross-team verification activities.BenefitsComprehensive medical, dental, and vision plansLife insurance and disability plan options401(k)RSUsESPPPaid company-selected holidays & floating holidaysPTO - generous time off programsCareer growth opportunities