SoC Physical Design Engineer, Top Level
$126.8k - $190.9kApple Inc.
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be responsible for implementing complete chip design from netlist to tapeout. Description Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle. Work with the physical design team to drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress. Be a focal point for place and route, drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. Minimum Qualifications Minimum BS with 0+ years experience. Preferred Qualifications Knowledgeable in partition or top level P&R implementation, including floorplanning, clock and power distribution, timing closure, physical and electrical verification. Experience with Top Level a plus, but not required. Strong knowledge of physical design construction and analysis flows and methodology. Experienced with industry standard tools, understanding their capabilities and underlying algorithms. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $126,800 and $190,900, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr Apple Inc.
$147.4k - $272.1k
...implementing complete chip design from netlist to tapeout... ...architecture and drive physical aspects early in the... ...among place and route engineers, set goals and milestones... ...different domains like top, STA, block place and... ...Experience with typical SoC issues such as multiple...SuggestedTemporary workRelocation- ...We are seeking a highly experienced Senior/Staff Physical Design Engineer specializing in Top-Level EMIR and Power Integrity Signoff for advanced-node SoC designs (5nm / 3nm / 2nm). The ideal candidate will have proven expertise in full-chip Static & Dynamic IR Drop analysis...Suggested
- ...We are seeking a Senior/Staff Physical Design Engineer with deep expertise in top-level clock architecture and CTS implementation for advanced-node SoCs (5nm / 3nm / 2nm). The ideal candidate will have strong experience designing large-scale clock distribution networks...Suggested
$181.1k - $318.4k
...directly responsible for the physical implementation of design partition(s) (from netlist... ...) for a highly complex SOC utilizing innovative process... ...Experience with partition level P&R implementation... ...Electrical/Electronics/Computer Engineering or related field. Experience...SuggestedRelocation$130k - $155k
...with the ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging our... ...AND BENEFITS: Pay range: Physical Design Engineer/Level I: $130,000.00 - $155,000.00/per year Physical Design...SuggestedPermanent employmentFull timeTemporary workWorldwideWeekend work- An established industry player is seeking a skilled Physical Design Engineer to join their innovative team. In this long-term contract role, you... ...complex design issues, and contribute to the integration of ASIC/SoC designs. If you have a passion for physical design and want...Long term contractRemote work
$181.1k - $318.4k
SoC Physical Design Methodology Engineer Description As a Physical Design Methodology engineer you will be an active participant in the team responsible for ensuring our physical design methodology is efficient, robust, and reliable. You will create and implement methodologies...Relocation- A leading technology company in California is looking for a Physical Design Engineer. This role involves collaborating with architecture and design teams, verifying and driving implementation of complex SOC designs, and resolving physical design flow issues. A Bachelor...
$126.8k - $190.9k
...groundbreaking Apple product! In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology. Description In Physical Design, you will be...InternshipRelocation$147.4k - $272.1k
SoC Physical Design Engineer, STA/Timing Join us to help deliver the next groundbreaking Apple product. In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using...Relocation package$140k - $170k
Credo is engineering the future of high-speed connectivity... ...a systems-level approach to... ...Cables (AECs) all designed for maximum performance... ...Role As a Senior Physical Design Engineer, you... ...for Credo SoC designs. This role... ...Responsibilities Lead and drive top-level, IP, and...Local area$120k - $160k
A cutting-edge technology company in San Jose is seeking a Physical Design Engineer to join its ASIC/SoC team. In this role, you will contribute to developing electro-optical engines and complex mixed-signal designs. Responsibilities include executing the full physical...- ...industries, national labs, and top-tier healthcare systems. In... ...inference services. 3D Physical Design Engineer Cerebras Systems builds... ...combination of traditional ASIC/SoC physical design skills,... ...~ Strong knowledge of block level and full-chip physical verification...Full time
- A high-speed connectivity firm in San Jose is seeking a Senior Physical Design Engineer. This role involves managing all aspects of physical design for SoC projects, focusing on optimization and methodology development. The ideal candidate has over 10 years of experience...
$2,000 per month
...hundreds of millions from top‑tier investors and staffed by leading engineers, Etched is redefining the... ...Summary We are seeking a Design Verification Engineer to... ...good fit if you have ASIC/SoC Design & Verification... ...Some exposure to kernel level performance metrics and profiling...Work at officeRelocation package- ...an adaptive, self‑motivated design verification engineer to join our growing team.... ...contributor, you will be part of a SOC team to drive and improve... ...at the core and SOC level Build testbench components... ...medical condition, mental or physical disability, national origin...
- ...the microarchitectural design and RTL implementation of Adaptive SoC and FPGA configuration system... ...analysis, verification, physical design integration, and... ...Work closely with test engineers to implement design-for-... ...and Makefile System level knowledge is a plus for...
$122.44k - $232.19k
**Welcome!**.Physical Design Engineer - Neuromorphic Computing page is loaded## Physical Design Engineer... ...of computing, from transistor-level innovation to software abstractions, join... ...considered a plus factor in identifying top candidates. Experience listed below would...InternshipLocal areaImmediate startShift work$110k - $160k
Are you a highly motivated and skilled Physical Design Engineer with at least 3 years of industrial experience eager to push the boundaries of... ...design flows from netlist‑to‑GDS, including: Block and SoC‑level floorplanning, power grid implementation, and low‑power structure...Internship$126.8k - $190.9k
...technology company in California is seeking a dedicated chip design engineer. You will implement chip design from netlist to tapeout, collaborating... ...ideal candidate holds a minimum BS degree with knowledge of physical design and related tools. This opportunity offers a...$2,000 per month
...Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the... ...Etched is looking for exceptional Physical Design engineers to join our team. In this role, you will own block-level implementation and verification,...Work at officeRelocation package$147.4k - $272.1k
...in San Jose is seeking an experienced professional for a chip design role focused on implementing complete design from netlist to tapeout... ...a BS degree, and a deep understanding of ASIC integration and physical design methodologies. The position offers a competitive base...- ...ROLE: Join AMD's Silicon Design team to design and... ...As a Senior ASIC Design Engineer, you will own the complete... ...is a seasoned ASIC/SOC designer with proven expertise... ..., timing closure, and physical design awareness. With... ...design roles. Expert‑level Verilog RTL coding...
$153.5k - $310.5k
## Sr. ASIC Physical Design EngineerApplylocations: San Jose, California, United States... ...HPE.**Job Description:**As a block-level Physical Design Engineer, you will contribute to all phases of... ...Implement physical design at the large SoC block level from RTL to GDSII,...Work experience placementWork at office2 days per week$108k - $167.5k
As a Senior Physical Design Engineer, you will be responsible for the physical design implementation PnR run, Performance/Power/Area (PPA) comparison... ...process nodes. Netlist-to-GDS flow including block/soc-level placement, clock tree synthesis, routing, and design...InternshipWork at officeFlexible hours$170k - $220k
...: We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs... ...constraint validation Chip/block-level floorplanning and pin assignment... ...pipeline of new technology projects for top companies. Employees are real...Local area$160k - $195k
...Discover more at . As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role... ...supporting or developing complex SoC/silicon products for Server, Storage, and... ...for technologies 7nm or less. Block level ownership from architecture to GDSII, driving...Full timeFlexible hours$154.84k - $232.26k
Staff Physical Design Engineer page is loaded## Staff Physical Design Engineerlocations: US, CA, San Jose... ....* Proven track record of driving **IP-level RTL-to-GDSII** implementation with... ...hierarchical design abstraction**, and **SoC IP integration**.* Exposure to **flow development...Permanent employmentFull timeWork at officeDay shift- ...and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces... ...specifications and write block and chip-level tests in C,SV,UVM ○ Debug RTL and Gate simulations and work with design engineers to verify fixes. ○ Write diagnostics...
- ...We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at... ...Preferred Qualifications: Proven experience with large-scale SoC or AI-class designs At least 5 years of PD experience...For contractors
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