Senior Physical Design Engineer - Tapeout Leader
Celero Communications
Celero Communications in Irvine, CA is seeking an experienced Physical Design Engineer to lead physical implementation of SoCs, including floorplanning, power planning, P&R, CTS, timing closure, and sign-off. Collaborate with architecture, RTL, circuit and verification teams to deliver high-performance chips; mentor engineers and define physical design methodologies to ensure tape-out of next-generation semiconductor products. #J-18808-Ljbffr
Vacancy posted 3 days ago
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