ASIC Verification Engineer
Rambus
Rambus seeks a Senior/Principal Design Verification Engineer to join the Memory Controller IP Verification team in Hillsboro, Oregon. The role involves pre-silicon RTL verification for DDR, HBM and GDDR DRAM controllers, with hybrid onsite flexibility. Responsibilities include testbench creation, coverage planning, regression testing, and verification environment scripting. Required: 10+ years HDL verification with SystemVerilog and DDR experience. #J-18808-Ljbffr Rambus
Vacancy posted 3 days ago
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