Design Verification Technical Architect (Santa Clara)

Job Requirements Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you.The achievers and courageous challenge-crushers we seek, have the following characteristics and skills:What You will Do:• Build State of Art Verification environment for IP,SS,SOC raning from Automotive to AI chips• Lead verification team and execution of different projects to completion• Hands on work in building verificaiton environment involving processors, high speed peripheral(PCIe,UCIe,DDR)• Work with cross functional(PD,DFT,Design,Emulation) team to resolve issue• Responsible for DV deliverables and DV closure meeting the required metrics like code coverage, functional coverageWhat You Will Bring:10+ YOE DV experience.Good hands on knowledge of SV-UVMExperience in leading teamExperience in building environment, verification plan, test planExperience in building re-usable verification environment for SS, SOCExperience with integrating third party VIPPython script expertiseUse of Source Control like git or equivalentHands on exp of at least on high speed protocol UCIe/PCIe5+/LPDDR5+/Ethernet200G+GLS exp Arm Core/C-Base expEmulation exp plus Multiple high speed protocol exp plus.Pay Range: $150K to $220KCompensation decisions are made based on factors including experience, skills, education, and other job-related factors, in accordance with our internal pay structure. We also offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.Work Experience VerilogSV-UVMPythonArm-Core/RISC-VCHigh speed protocol such as UCIe/PCIe5+/LPDDR5+/Ethernet200G+AMBA protocolVerifcation environment setup exp at SS/SOC levelPlanning execution of entire projectIntegrating and using third party VIPExcellent communication skill and work in global environmentBenefits Benefits:401(k)401(k) matching Dental insuranceHealth insuranceLife insurancePaid time offReferral programVision insuranceShort/Long Term DisabilityJob SummaryJob number: P-119214Date posted : 2026-05-29Profession: SemiconductorsEmployment type: Full-TimeExperience: VerilogSV-UVMPythonArm-Core/RISC-VCHigh speed protocol such as UCIe/PCIe5+/LPDDR5+/Ethernet200G+AMBA protocolVerifcation environment setup exp at SS/SOC levelPlanning execution of entire projectIntegrating and using third party VIPExcellent communication skill and work in global environment