Principal RTL Design Engineer - PCIe / CXL / High-Speed SoC (Santa Clara)

Job Title: Principal RTL Design Engineer - PCIe / CXL / High-Speed SoCLocation: Santa Clara, CACompensation: $200K - $250K base DOE plus bonus and RSUs ($300K - $350K+ total comp.)Requirements: RTL Design, Verilog / SystemVerilog, PCIe / CXL / Ethernet / UALink, High-Speed SoC DesignPosition OverviewAs a Sr. Staff or Principal RTL Design Engineer, you will join the Connectivity Business Unit within the Data Center Group (DCG), contributing to the development of advanced silicon solutions for next-generation data center infrastructure. In this role, you will be instrumental in driving the design and delivery of high-performance ASICs that power industry-leading products for hyperscale and enterprise customers. This position offers the opportunity to work alongside world-class engineers, influence key design methodologies, and contribute to cutting-edge technologies in an environment that values innovation, collaboration, and execution excellence.Key ResponsibilitiesOwn and implement RTL design blocks, demonstrating strong RTL coding expertise.Collaborate with the architecture team to understand and define feature enhancements.Translate specifications into efficient RTL implementations.Ensure all design quality standards and criteria are consistently met.Partner with physical design teams to review timing reports, perform STA, write SDC constraints, analyze power, and provide guidance on floorplanning and timing closure.Work closely with the verification team on pre-silicon activities, including test plan reviews, coverage analysis, simulations (block and full-chip), performance evaluation, and debugging; strong debug skills are essential.Define subsystem microarchitecture and register specifications for complex SoCs, and contribute to specification development.Lead and participate in detailed reviews of performance, architecture, and design requirements with cross-functional teams, IP vendors, and customers.Contribute to the development and evaluation of design and verification methodologies, and help enhance existing processes.Collaborate with post-silicon and software and firmware teams to support silicon bring-up and performance optimization.QualificationsBachelor's degree in Electrical Engineering or a related field with 15+ years of relevant experience, or a Master's/PhD with 12+ years of experience.Strong proficiency in Verilog/SystemVerilog RTL development, including SystemVerilog assertions.Experience working on complex subsystems, IPs, or switch SoCs involving PCIe, CXL, Ethernet, or UALink.Deep knowledge of PCIe, CXL, Ethernet, or UALink protocols.Expertise in microarchitecture development and translating requirements into robust designs.Proven ability to collaborate effectively with third-party IP vendors and customers.Extensive experience in RTL design, synthesis, constraint development, static timing analysis, debugging, block-level functional verification, logical equivalence checking, and CDC/RDC.Solid experience with implementation and timing closure for high-speed designs.Hands-on experience across the full chip development lifecycle, with strong proficiency in front-end and mid-end design tools and methodologies.BenefitsComprehensive medical, dental, and vision plansLife insurance and disability plan options401(k)RSUsESPPPaid company-selected holidays & floating holidaysPTO - generous time off programsCareer growth opportunities