VP of SoC Architecture (AI & Memory Systems) (Santa Clara)

Job Title: VP of SoC Architecture (AI & Memory Systems)Job Location: Santa Clara, CA, or Boston, MACompensation: $300K - $400K base DOE plus equityRequirements: SoC Architecture Leadership, CXL / UALink / ESUN, Memory Expansion, NIC / SmartNIC / DPU / IPU, DDR Memory Subsystems, AI Systems ArchitecturePosition OverviewWe are seeking a VP of Architecture to design our flagship silicon product. You will be working in collaboration with the software and ASIC design teams to put together the SoC and system architecture for our memory expansion device.Key ResponsibilitiesArchitecting an efficient high-bandwidth memory expansion device for scale-up networks.Growing the underlying team of SoC architects, system architects, and performance modeling engineers.Collaborate closely with the software/workload team to define an efficient architecture and system for solving the memory capacity bottlenecks for AI infrastructures.QualificationsBachelor's (Master's or PhD preferred) in Electrical Engineering, Computer Engineering, or related field.Track record architecting commercially successful data movement silicon, e.g., NICs, SmartNICs, IPU/DPU, CXL devices; ideally supporting memory semantics over the fabric.Strong background in high-bandwidth and scale-up networks.Experience architecting CXL/UALink/ESUN endpoints.Strong understanding of DDR-based memory subsystems.Experience building high-speed data movement SoCs.Preferred Qualifications (optional)Familiarity with ML systems and networks is a strong plus.Familiarity with NVLink internals is a strong plus.BenefitsCompetitive salary commensurate with experience including base salary, performance-based bonus, and early-stage equity grantComprehensive benefits including health, dental, vision, and life insuranceWell-equipped, sunny offices in Santa Clara, CA and Boston, MARelocation assistance and visa sponsorshipPerks include a daily lunch stipend, 401k match, and moreA collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing