Mixed Signal IP Verification Engineer

Overview Join Intel as a Mixed Signal Design Verification Engineer and play a crucial role in shaping the future of cutting‑edge technology. In this role, you will ensure Intel's mixed signal logic components meet the highest standards of functionality, performance, and reliability. Your work will directly contribute to the design of advanced architectures and technologies that power tomorrow's innovations. Responsibilities Develop and execute comprehensive verification plans for mixed signal logic components to ensure alignment with microarchitecture specifications. Design and implement test benches and verification environments using advanced methodologies such as OVM and UVM. Perform system‑level simulation to verify functionality, analyze power and timing, and identify potential design issues. Collaborate with digital and analog architects, RTL developers and physical design teams to optimize verification strategies and meet performance, power and functional goals. Debug presilicon issues by replicating, root‑causing and implementing corrective measures for failing tests. Create and maintain analog behavioral models and contribute to the development of reusable verification infrastructure and methodologies. Document test plans, verification results and drive technical reviews with design and architecture teams. Desired Behavioral Traits Exceptional problem‑solving skills and willingness to debug complex presilicon issues. Strong collaboration and communication skills with a track record of working effectively with cross‑functional teams. Passion for innovation and a commitment to excellence in engineering. Qualifications Minimum: Bachelor’s or BS degree (or equivalent) in a specialized field with at least 3 years of relevant experience, or Master’s degree (or equivalent) with at least 2 years of relevant experience, or PhD (or equivalent) with at least 1 year of relevant experience. Experience with verification methodologies such as OVM and UVM. Experience with SystemVerilog and Verilog for test environment and design verification. Experience developing test environments for the functional verification of mixed signal logic components. Preferred Qualifications Experience with power intent design and/or UPF (Unified Power Format) modeling. Benefits Competitive pay and stock bonuses. Health, retirement and vacation benefits. Compensation Annual salary range for U.S. positions: $122,440.00 – $232,190.00. Work Model This role is eligible for a hybrid work model, allowing employees to split their time between on-site and off‑site work at the assigned Intel site. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation or ordinance. #J-18808-Ljbffr Intel Corporation