Workload / Performance Model Lead

Job Description SiFive, a leader in RISC‑V CPU IPs, is seeking an experienced leader to head benchmarking and performance infrastructure development. The candidate will guide the performance team in creating benchmarks for evaluating CPU and accelerator performance, and develop and deploy the tools necessary for architecture development and evaluation. Responsibilities Identify, prepare (develop or port and set up), and analyze performance for processor/accelerator development. Analyze performance bottlenecks in micro‑architecture and software stack. Develop innovative methods to characterize workloads on simulators, emulators and/or hardware platforms. Develop performance projection methodology for complex workloads. Build and deploy efficient tools and infrastructure for performance evaluation. Requirements MS or PhD in Computer Science / Computer Architecture. 10+ years of direct industry experience with performance simulation tools—from ISA to SoC/system simulators; from analytical to cycle‑based models; and from bare‑metal environments to virtual machines. 5+ years delivering hardware or software products as part of an engineering team. Strong foundation in computer architecture of high‑performance out‑of‑order CPU designs. Awareness of industry micro‑architectures is a plus. Expertise in workload characterization to identify hardware/software performance bottlenecks. Proficiency in workload reduction techniques for efficient performance simulation and projection. Competency in software engineering best practices to maintain and refactor large object‑oriented codebases. Strong object‑oriented programming skills—including encapsulation, class coherency, inheritance, and polymorphism. Discrete Event Simulation (DES) competency, especially with DES modeling techniques and best practices. Ability to independently analyze performance bottlenecks in micro‑architecture and software stack. Awareness of potential security holes is a plus. Desirable Hands‑on expertise with hardware development (RTL/implementation flows, verification/validation, backend flows, FPGA flows) or software development (C/assembly, OS/RTOS, IDEs, compilers/debuggers). FPGA debug experience, including using Integrated Logic Analyzer for waveform capture and debugging. Familiarity with Git and branching/forking methodologies. Benefits Pay and benefits are consistent with SiFive values and applicable law. The base pay range for this role is $231,444.00–$282,876.00, varying by location and dependent on experience and qualifications. In addition to base pay, the role may be eligible for variable/incentive compensation and/or equity. The comprehensive benefits package may include healthcare and retirement plans, paid time off, and more. Additional Information This position requires successful background and reference checks and satisfactory proof of right to work in the United States. Employment offers are contingent on compliance with export‑control laws and the Company’s ability to obtain necessary export licenses or approvals. Equal Opportunity Employer SiFive is an equal‑opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use this system to confirm employment eligibility of all new hires in accordance with federal law. All applicants will complete a Form I‑9 upon hire. California residents: see the provided job candidate notice for information on how we handle personal information and privacy rights. #J-18808-Ljbffr SiFive, Inc.