Senior FPGA/DSP Design Engineer

Title: Senior FPGA/DSP Design Engineer (Direct Hire – No Recruiters)

Location: Torrance, CA (full-time on-site, 9/80 schedule option)

Company Description

Great people working together in a relaxed, positive environment, solving challenging engineering problems while developing world-class products.

Founded in 1998, Escape Communications designs, produces and sells complex wireless communications products and systems into the telecommunications and SATCOM equipment industries, in both commercial and military markets.

We are located in the South Bay area, a few short miles from Los Angeles County beaches. Escape is a small company, where employees get the opportunity to play a critical role in the development and delivery of world-class products to companies across the globe. We are growing, and we are looking for exceptional, motivated individuals to grow with us.

For more details, visit

Job Description

Escape Communications develops state-of-the-art signal processing platforms for satellite communications systems, as well as terrestrial microwave and millimeterwave wireless radio links. These platforms employ highly flexible architectures, with configurable modulation modes ranging from FSK to 4096QAM, and configurable bit rates ranging up to 10 gigabits per second and beyond, and advanced packet processing features. Advanced features include cross-polarization interference canceling, adaptive modulation & coding, and advanced forward error correction. Our military SATCOM terminal platform products employ complex protected frequency hopped, time permuted TDMA waveforms. Applications include protected military satellite communications, high-capacity commercial satellite communications, cellular backhaul, broadband wireless access backhaul, high capacity last mile, and private networks.

Escape is seeking a talented and motivated individual to play a key role FPGA implementation on our radio modem products. Responsibilities include:

• Design and implementation of FPGA-based digital signal processing systems
• Development of self-checking unit/system-level test benches
• Troubleshooting and resolving design issues

Qualifications

The position requires RTL design experience (VHDL preferred). The following skillsets are also required:

• Understanding of FPGA design flow (synthesis, place & route, etc)
• Experience with full development cycle of FPGA design
• Understanding of hardware architecture
• Strong understanding of software and hardware interaction
• Ability to read and understand schematic designs
• Basic working knowledge of lab equipment such as oscilloscopes, spectrum analyzers, signal sources, power supplies
• Excellent verbal and written skills to interact with design teams
• Xilinx and/or Altera Tool Suites

The following skillsets are desired, although not strictly required:

• Use of Subversion for codebase control in team environment
• Use of ModelSim/QuestaSim for FPGA design simulation
• Experience with script languages (Python, Perl, Ruby, etc.)

A bachelor’s degree in EE or CS is required; a master’s degree is strongly preferred. Preference will be given to applicants with prior relevant experience.

Successful applicant must be able to provide proof of authorization to work full-time in the US without visa sponsorship.

Compensation

Base Salary Range: $160,000 to $240,000 per year

The exact base salary will be determined based on the candidate's specific depth of VHDL, FPGA hardware implementation, and digital signal processing (DSP) verification experience.

Benefits

Escape Communications offers a relaxed work environment and a generous benefits package, including health benefits, long-term disability insurance, flexible vacation time, a 401K retirement plan, flexible work schedule (9/80), and a stock options plan for qualified applicants.

Escape Communications is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, or national origin.