Senior DFT Engineer - ASIC ATPG & Scan Optimization
Mirafra Technology
A leading software service organization in Tempe, Arizona seeks a qualified individual with extensive experience in design for test (DFT) for ASICs. The ideal candidate will possess at least 10 years of DFT experience for large scale ASICs and knowledge of Mentor Graphics tools. Responsibilities include generating ATPG, analyzing coverage results, and running gate simulations to verify functionality. Competitive compensation and a dynamic work environment are offered. #J-18808-Ljbffr Mirafra Technology
Vacancy posted 1 day ago
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