FPGA Design Engineer III

ABOUT FIREFLY AEROSPACE

Firefly Aerospace is a space and defense technology company on a mission to reliably and repeatedly launch, land, and operate space systems from Earth to the Moon and beyond. As the partner of choice for critical space missions, Firefly is the first commercial company to launch a satellite to orbit with 24‑hour notice and the first company to achieve a successful Moon landing. Headquartered in north Austin, Texas, Firefly is looking for passionate, hardworking innovators to join our team and help fuel our successful trajectory into space.

SUMMARY

Firefly is seeking an experienced FPGA RTL Design Engineer with 3+ years of direct professional Verilog hardware design experience. This role focuses on designing, implementing, verifying, and optimizing custom digital logic in the FPGA fabric of Microchip PolarFire SoCs for high‑reliability embedded systems. Key aspects of the work include RTL development, synthesis, timing closure, testbench creation, and integration of custom IP blocks with the integrated RISC‑V processor subsystem. This is a hardware design role — candidates should have meaningful hands‑on experience taking designs from RTL through implementation on FPGA hardware. You will work in a fast‑paced, collaborative environment to deliver robust firmware for mission‑critical space applications in industries such as aerospace, defense, and industrial automation.

RESPONSIBILITIES

Design, develop, and verify FPGA logic using VHDL/Verilog/SystemVerilog for Microchip PolarFire SoCs, including programmable logic, DSP blocks, and high‑speed interfaces (e.g., PCIe, Ethernet, SERDES). Create and optimize IP cores and custom peripherals/accelerators tailored to PolarFire's architecture. Integrate FPGA firmware with embedded processors (e.g., RISC‑V cores) and collaborate with software teams to support Board Support Packages (BSPs) and Linux kernel drivers. Build RTL verification environments with testbenches using UVM methodologies for design correctness and coverage. Perform functional verification, simulation, regression testing, and coverage analysis (e.g., functional, code, assertion). Conduct synthesis, place‑and‑route, timing analysis, and debugging using tools like Libero SoC, logic analyzers, and oscilloscopes. Implement radiation‑tolerant and fault‑tolerant designs for space‑grade applications. Develop automated test benches and CI pipelines for verification, including hardware‑in‑the‑loop testing. Contribute to system architecture, security, and real‑time processing requirements. Participate in code reviews, documentation, and stay updated on FPGA technologies and open‑source contributions.

QUALIFICATIONS

Required: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 3–5 years of professional RTL design experience using Verilog for FPGAs Demonstrated experience with the full FPGA design flow: RTL coding, simulation, synthesis, place‑and‑route, and static timing analysis Proficiency with at least one major FPGA tool suite (Xilinx Vivado or Intel Quartus) Solid understanding of synchronous digital design, clock domain crossing, finite state machines, and resource/timing optimization Preferred: Microchip Libero SoC Firefly offers outstanding benefits for our employees, including generous health, dental and vision plans with low plan deductibles, parental leave, educational reimbursement, short term disability, and flexible PTO options. To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Firefly Aerospace, Inc. is an Equal Opportunity Employer; employment with Firefly is governed based on merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status #J-18808-Ljbffr Cedarparktexasedc