Senior ASIC Verification Engineer

Functional Verification Engineer

Pay Range: $104.47hr - $110.27hr

Job Overview:

The candidate will participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. As part of a team of design and verification engineers, the successful candidate will work closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. The candidate will be responsible for carefully documenting and executing test plans consisting of directed and constrained-random tests to be run during simulation. The successful candidate is expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects. Familiarity with hardware modeling and/or assertion-based verification methods is required.

Experience and Education:

• 10+ years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting.
• Strong background in C/C++ development in a Linux environment.
• Strong debug skills and experience with debug tools such as Gdb, Valgrind.
• Proficient in Object Oriented programming, STL, computer architecture and data structures.
• Knowledge of Perl and Makefiles.
• Experience in Verilog/SystemVerilog/SystemC is preferred.
• Experience in C/Verilog environment using DPI/PLI is preferred.
• Strong analytical skills and attention to detail.
• Excellent written and communication skills.