Senior Design Verification Engineer

Design Verification Engineer

We are seeking an experienced Design Verification Engineer to support the development and verification of high-performance IPs, including compute arrays, DMA engines, Networks-on-Chip (NoCs), crossbars, and memory subsystems.

The ideal candidate will have strong hands-on experience developing and maintaining scalable SystemVerilog/UVM testbenches, along with deep knowledge of AXI protocols, performance verification, regression analysis, and coverage closure.

This program is already in execution, so we are looking for someone who can quickly integrate into the team and contribute in a fast-paced environment with evolving processes and limited documentation.

Key Responsibilities

Develop, enhance, and maintain scalable SystemVerilog/UVM verification environments and testbenches for complex, high-performance IP. Perform verification of AXI-based interfaces, NoC/Crossbar architectures, DMA engines, compute arrays, and memory subsystems. Develop verification strategies focused on functional correctness, performance, and system-level behavior. Execute and analyze regression testing, including failure triage, debugging, and root-cause analysis.

• Drive functional and code coverage closure and support overall verification sign-off.
• Identify performance bottlenecks and validate performance requirements across complex IP and subsystem designs.
• Work effectively within established customer tools, flows, and verification methodologies.
• Adapt quickly in a fast-moving environment where processes and documentation may still be evolving.
• Collaborate with verification, design, architecture, and other engineering teams to achieve verification milestones.
• Provide clear daily and/or weekly progress updates to customer and project stakeholders.
• Support overall verification closure and ensure high-quality project delivery.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• 5–15 years of relevant experience in ASIC design verification, SoC verification, or a related field.
• Strong hands-on expertise with SystemVerilog and UVM.
• Experience developing and maintaining complex, scalable UVM testbench environments.
• Strong knowledge of AMBA AXI protocols and interface verification.
• Experience verifying NoC, Crossbar, DMA, compute, and/or memory subsystem architectures.
• Strong experience with regression execution, failure triage, debugging, and coverage closure.
• Experience with performance-focused verification and analysis.
• Working knowledge of scripting and automation using Python, Perl, Make, or similar tools.
• Strong debugging, analytical, and problem-solving skills.
• Ability to work independently and contribute effectively within a highly technical engineering team.
• Strong written and verbal communication skills, including the ability to communicate technical progress and issues effectively to customer stakeholders.
• Experience working on large-scale ASIC/SoC verification programs.
• Experience with high-performance compute, networking, or memory-related IP.
• Experience working in fast-paced or start-up-style engineering environments.
• Familiarity with customer-specific verification tools, flows, and methodologies.
• Demonstrated ability to drive verification activities through coverage and sign-off closure.

Nesco Resource offers a comprehensive benefits package for our associates, which includes a MEC (Minimum Essential Coverage) plan that encompasses Medical, Vision, Dental, 401K, and EAP (Employee Assistance Program) services. Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.