Design Verification Engineer
Omega Solutions
Design Verification Engineer
Location: Sunnyvale, CA Rate: 50/hr W2 Client is Microsoft
Required:
- 7+ years of ASIC verification experience
- UVM/System Verilog
- VCS simulator, Verdi
- 2, 3 projects experience with UVM based testbench, coverage closure
Desirable:
- Previous experience with PCIe, Ethernet, HBM-DDR, Processor verification, floating point computational unit highly desired
- C/C++ experience is desired
- Scripting skills(Perl, Python)
- Formal verification experience is a plus
Vacancy posted 3 days ago
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