Design Verification Engineer, Coherent Interconnect

Position SummarySamsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us!Role and ResponsibilitiesAs a Design Verification Engineer, you will contribute to the verification of System IP, including coherent interconnects and caches. The ideal candidate will have a background in design verification, testbench architecture, and knowledge in methodologies across both block- and top-level environments. You will execute verification strategy, implement best practices, and support project goals in collaboration with global cross-functional teams to advance Samsung’s cutting-edge coherent interconnect IPs that power next-generation consumer mobile products.You develop and maintain deep expertise in microarchitecture and design verification for coherent interconnect IPs to develop, verify, and optimize high-performance, low-latency interconnect solutions that meet the needs of complex SoC designs.You play a role in architecting, developing, and maintaining reusable verification environments and testbenches from scratch, including stimulus, assertions, checkers, covergroups, and SystemVerilog constraints.You support design excellence and thorough verification of key features by contributing to test plans, verifying feature correctness, performing code and spec reviews, debugging functional failures from regressions to identify root cause, and performing coverage analysis to identify gaps and propose improvements.You contribute to defining new verification methodologies, improving flows and productivity, and adopting advanced practices such as power-aware verification with UPF and gate-level simulations.You collaborate with design, SoC, physical design, and performance verification teams to analyze and debug failures, resolve spec issues, and enable successful bring-up across IP, SoC, and silicon.You take initiative on moderate-to-complex projects and contribute to a high-performing team culture by communicating openly and exercising data-driven decision making.Skills and Qualifications10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years of experience with a Master’s Degree, or 6+ years of experience with a Ph.D.8+ years of professional experience in a design verification role building testbenches from scratchStrong background in design verification of coherent interconnects, combined experience with LPDDR memory controllers is a plusProficiency in ARM protocols – CHI, AXI, ACElite, APBStrong coding skills in System Verilog, UVMExperience with Git version control, Unix/Perl scriptingFormal verification skills will be a plusStrong communication and collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment.Our Team The System IP & SoC Architecture team at SARC/ACL designs proprietary coherent interconnects and memory controllers that power Exynos SoCs for Samsung’s premium consumer devices. We play a critical role in shaping the technology roadmap, delivering scalable, performance- and power-optimized IP solutions that support advanced system modeling and real-world applications such as gaming and computational photography. With scalability and efficiency at the core of our designs, our IP integrates seamlessly into complex semiconductor products, enabling cutting-edge memory subsystem capabilities across diverse market segments.Joining our team means collaborating alongside talented engineers from diverse technical backgrounds across a global organization. You’ll have the opportunity to build next-generation technologies, broaden your expertise, and solve impactful challenges in a supportive environment built on collaboration, continuous learning, and growth.Total RewardsAt Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $151,000 and $251,800. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.Additionally, this role might be eligible to participate in long term incentive plan and relocation.This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).Trade Secrets By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.U.S. Export Control This role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.#SARC #ACL* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.* Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.SummaryLocation: 3900 N Capital of Texas Hwy, Austin, TX, USA; 3655 N 1st St, San Jose, CA, USAType: Full time