Principal Silicon Design Verification Engineer

Job ID: 200038893Posted: 2026-10-05Location: United States, California, Santa ClaraSalary: USD $142,800 - $274,800 per yearEmployment type: Full-TimeWork site: 3 days / week in-officeRole type: Individual ContributorTravel: Less than 25%Profession: Hardware EngineeringDiscipline: Silicon EngineeringCompany: MicrosoftOverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide.#azurehwjobs#SCHIEResponsibilitiesAs a Principal Engineer - ASIC verification in the Data Processing Unit team you will be validating silicon to solve complex problems in a datacenter. You will interact with the architecture team to develop a programmable silicon implementation. This position is expected to be highly visible and impactful. The vast breadth of domains required to build our DPU silicon gives the perfect opportunity to experience different areas of expertise. The depth required to solve complex engineering problems utilizes your experience and provides you with the perfect platform to shine and grow to the next stage in your career. Responsibilities: As a Principal Engineer in the Data Processing Unit team, you will be validating silicon to solve complex problems in a datacenter.Lead key components of functional validation of complex ASIC SOC using UVM/C test benchPerform pre-silicon SoC verification, post-silicon validation by defining testing strategiesWork with cross functional teams, architecture, design, verification, partner teams for project execution and influence next generation designsDevelop test plan, C tests and infrastructure to complete functional validation of complex design and report bug/issuesRunning tests, debugging failures, creating stress and performance scenarios to meet test plan goalsActively participate in chip bring up and write test firmware to support various teamsInnovate to improve validation efficiency through methodologies and toolsCoach and mentor others in your areas of expertiseDemonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & InclusionQualificationsRequired Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.Other QualificationsAbility to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.Preferred Qualifications10+ years of experience in pre-silicon validation with a proven track record of delivering high performance Network switches/accelerators, Central Processing Unit (CPU), Vector processors and Graphics Processing Unit (GPU’s) or relevant experience.Experience in UVM/C verification methodologyKnowledge of Ethernet, TCP/IP, ROCEv2, MAC/PCS, Networking NIC/Switches.Proven track record with the definition and development of complex SoCs. In depth understanding of processors and peripheral interconnect bus protocols and architectures proficiency in Verilog, System Verilog, and UVM based testbench environment.Experience building UVM testbenches, managing regressions, meeting code coverage and functional coverage goals to successful tapeout.#azurehwjobs#SCHIESilicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.