Design Verification Engineer
Redolent
Design Verification Engineer
We are seeking a skilled Design Verification Engineer to join our hardware engineering team. The ideal candidate will be responsible for verifying complex digital designs using advanced verification methodologies to ensure high-quality silicon delivery.
Key Responsibilities:
- Develop and execute verification plans for digital IPs or SoCs.
- Write and maintain testbenches using SystemVerilog/UVM.
- Perform simulation-based verification, debugging, and regression testing.
- Collaborate with design, architecture, and firmware teams to resolve issues.
- Review specifications, contribute to test coverage analysis, and ensure completeness.
Required Skills:
- Proficiency in SystemVerilog and UVM methodology.
- Solid understanding of digital design fundamentals (RTL, timing, clocking).
- Experience with EDA tools (e.g., VCS, Questa, Verdi, SimVision).
- Familiarity with scripting languages (Python, Perl, TCL).
- Strong debugging and problem-solving skills.
- Excellent communication and teamwork abilities.
Preferred:
- Experience with SoC-level verification, assertion-based verification, or formal verification.
- Knowledge of AMBA protocols (AXI, AHB, APB).
Vacancy posted 3 days ago
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