Full-Chip Physical Design Verification Engineer
$100kTenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you.This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.Who You AreA seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.A mentor and technical leader passionate about building efficient, manufacturable silicon.What We NeedBS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verification experience.Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.Scripting proficiency in Python and TCL for automation and flow optimization.What You Will LearnAdvanced physical verification methodologies and flow optimization for next-generation SoCs.Integration and verification strategies for full-chip signoff across advanced process technologies.Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.Leadership and mentoring opportunities in building scalable PV methodologies and automation.Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
$2,000 per month
...frontier intelligence. We co-design chips, racks, software, and... ...investors and staffed by leading engineers, Etched is redefining the... ...PD engineer, you will own full-chip implementation—encompassing... ...clocking, timing analysis, physical verification, and sign-offs—from...SuggestedWork at officeRelocation package$165k - $241.4k
...Wireless products. We design networking... ...in the ASIC design verification for Cisco high-end... ...functional coverage, multi-chip/system simulation,... ...science/computer engineering/related degree and... ...blocks/clusters/full chip level for... ...together across the physical and digital worlds...SuggestedFull timeTemporary workLocal areaWorldwideFlexible hours$97.7k - $182.62k
...poster from Capgemini Engineering About the Job You're... ...forward-thinking team as a Design Verification Engineer,... ...of advanced System-on-Chip (SoC) designs that integrate... ...convergence of the physical and digital worlds. Coupled... ..., or commission. Full time regular...Suggested16 hoursFull timeLocal area$167.7k - $245.2k
...each other grow. Because full product development—from design to qualification to... ...quickly. As an ASIC Design Verification Engineer, you will play a critical... ...functional coverage, multi-chip/system simulation, post... ...together across the physical and digital worlds. These...SuggestedFull timeTemporary workLocal areaFlexible hours$116k - $246k
...faster than ever.Job Description:As a Design and Verification Engineer on Micron’s Pathfinding Design Team,... ...memory solutions, beginning with full-chip functional verification and expanding... ...design.Strong knowledge of semiconductor physics, electronic circuits, and circuit-...SuggestedFull timeLocal areaImmediate start$200k - $250k
Job Title: Principal Design Verification Engineer - PCIe / High-Speed SoCLocation: Santa Clara, CACompensation... ..., SerDes, UALink, interconnect) and full-chip integrations, drive closure of... ...designers, firmware/driver teams (ARM), and physical design to resolve verification issues...$158.6k - $317.8k
...infrastructure technology, designing advanced chip solutions that power high-performance... ...With a strong focus on engineering excellence, cutting-edge... ...a Principal Design Verification Engineer to join a high-performing... ...600 – $317,800 annually Full benefits package (medical,...Full timeWorldwide$134.39k - $201.3k
...reusable components, verification environments, and... ...the COE, you will design, verify, and... ...most advanced custom chips for hyperscale cloud... ...in electrical engineering, Computer Engineering... ...support, mental and physical health, and... ...SummaryLocation: Santa Clara, CAType: Full timePermanent employmentFull timeInternshipWork from homeShift work$214.1k - $309.8k
...solutions for data centers by designing some of the most complex chips being developed in the... ...the opportunity to get full exposure to all aspects of... ...Impact:As an ASIC Design Verification Leader, you will play a... ...work together across the physical and digital worlds. These...Full timeTemporary workLocal areaFlexible hours$127.63k - $191.2k
...experienced Senior Staff Level Physical Verification CAD Engineer to join our dynamic team.... ...context of semiconductor design and manufacturing. This role... ...include some usage of full custom layout tools to review... ...for efficient and reliable chip design, from physical verification...Permanent employmentFull timeInternshipWork from home$122.44k - $232.19k
...work every single day to design and manufacture silicon... ...series of research chips pioneered event-driven,... ...power the coming era of physical AI systems-beyond the reach... ...physical design engineers passionate about innovation... ...Santa Clara; US, California, San JoseType: Full timeFull timeInternshipLocal areaImmediate startShift work$136k - $218.5k
...intelligence.We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. If you... ...power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as...Full timeShift work$168k - $264.5k
...for best-in-class Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join... ...and innovative chips, enjoy working in a meaningful... ...noise analysis and back-end verification across multiple projects along... ...Santa Clara; US, TX, Austin; US, OR, HillsboroType: Full timeFull time$163k - $237k
Participate in the Physical Design of complex blocks.Contribute to the design and closure of the full chip and individual blocks from RTL-to... ...Bachelor's degree in Electrical Engineering, Computer Engineering,... ...leverage your design and verification expertise to verify...Worldwide$168k - $264.5k
...are now looking for a Senior Physical Design Engineer. NVIDIA has continuously... ...methodologies, flow automation, chip floorplan, power/clock... ...noise analysis and back-end verification.What we need to see:BSEE (MSEE... ...: US, CA, Santa Clara; US, TX, AustinType: Full timeFull time$136k - $218.5k
...on the world.We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge... ..., LPUs and SoCs at block level, cluster level, and/or full chip level.Help in driving frontend and backend...Full time$164.47k - $311.89k
Job Details:Job Description: As a Physical Design Timing Engineer, you will play a pivotal role in shaping the... ...of Intel's cutting-edge System-on-Chip (SoC) designs. Your expertise will directly... ...closely with the clocking team and full-chip designers to balance timing fixes...Full timeInternshipLocal areaImmediate startShift work$170k - $220k
...description: We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our... ...and delivers advanced System-on-Chip solutions across multiple emerging technologies... ...as part of a small team. Will work of full project lifecycle from inception to...Local area$116k - $166k
Participate in the Physical Design (PD) of blocks for complex TPU chips.Contribute to the design and... ...s degree in Electrical Engineering, Computer Engineering,... ...leverage your design and verification expertise to verify... ...(DFT), Floorplan, and full-chip Signoff teams. Additionally...Worldwide$168k - $264.5k
...impact on the world.We are looking for a physical design engineer to be a part of NVIDIA’s physical... ...gaming and more. As the cadence of NVIDIA’s chip cycle shortens, it poses new challenges... ...US, CA, Santa Clara; US, TX, Austin; US, TX, Remote; US, CA, RemoteType: Full timeFull timeRemote work$183k - $247.6k
Annapurna Labs designs silicon and software that accelerates... .... Our custom chips, accelerators, and... ...looking for an ASIC Physical Design Engineer to help us trail-blaze... ...responsibilities- Drive full chip floorplan,... ...-generation physical verification and integration methodologies...Local areaFlexible hours$230k - $280k
...builds the world's largest AI chip, 56 times larger than GPUs. This... ...a member of our tight knit physical design team, you will be working on the... ...:10+ years of physical design/verification experience.Strong knowledge of block level and full-chip physical verification...$141.91k - $200.34k
...About the RoleJoin the Design Technology Platform (... ...as part of the X-Chip SoC Full-Chip Integration team... ...to the development of physical design methodologies... ...issues uncovered by verification toolsWorking with tool... ...degree in electrical engineering or related field with...Full timeWork experience placementLocal areaImmediate startShift work$183k - $247.6k
...services.We are seeking an experienced Sr. Physical Design STA Engineer to build the next generation of our... ...& maintain flows for block and full-chip level static timing analysis• Write,... ...-off activities (ir/em, physical verification, DFT)Preferred qualification - Experience...Full timeLocal areaFlexible hours- Position:Physical Design Engineer II (eInfochips Inc)Job Description:What You'll... ...partitions of ASIC chip adhering to strict schedules... ...IR, drive LEC and physical verification signoff for your partitions... ...California (eInfochips)Time Type:Full timeJob Category:Engineering...Full timeWork at office
$100k
...an exceptional Senior-level Physical Design Engineer to drive top-level... ...complex AI and CPU System-on-Chip designs. You'll orchestrate... ...managing the complexity of full-chip physical design and want... .../IR analysis, and physical verification at the chip level.What You...Permanent employment$120k - $250k
...efficiently as allowed by physics, bringing the world... ...is seeking silicon verification engineers to join our team as we... ...execution at subsystem and chip-level and create... ...milestones including design freeze and tapeoutWho... ...base salary for this full-time position is determined...Full timeWork experience placementLocal areaRemote workMonday to FridayFlexible hours$141.91k - $200.34k
...:Job Description: Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this... ...verification- Exposure to RTL concepts, physical design, or CAD tool flows- Prior work... ...to your recruiter.SummaryLocation: US, California, Santa ClaraType: Full timeFull timeLocal areaImmediate startShift work$106.4k - $172.15k
...most of our teams work from the office full time, with flexibility when it’s... ...outcomes.Job SummaryYour Career As a Design Verification engineer on the ASIC team, you will ensure that... ...medical condition, national origin, physical or mental disability, political affiliation...Full timeCasual workWork at office$141.91k - $200.34k
...We work every single day to design and manufacture silicon products... ...wonderful.As an IP Verification Engineer, you will be working on UCIe... ...national origin, ancestry, age, physical or mental disability, medical... ...California, Santa Clara; US, Oregon, HillsboroType: Full timeFull timeWork experience placementLocal areaImmediate startShift work
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