SOC Top Level Physical Design Engineer, Annapurna Labs
$183k - $247.6kAmazon Locker
Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.Key job responsibilities- Drive full chip floorplan, placement, integration, PV signoff and tapeout- Collaborate with FE team to understand RTL and drive physical aspects early in design cycle- Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (FC, Calibre, IC Validator)- Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification- Debug and resolve physical verification issues in collaboration with layout and design teams- Interface with foundries for MT form, rule deck updates and violation waivers; Develop and maintain verification runsets and methodologies- Mentor junior engineers on physical verification methodologies and closureBasic qualifications- Experience scripting with Python, Perl, Bash or PowerShell- BS + 10yrs or MS + 7yrs in EE/CS, or related field- 5+ in physical verification for advanced technology nodes- Design Flow Knowledge: Understanding of backend physical design flows for chip-top/subsystems (FC/Innovus)- Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS)- Strong understanding of semiconductor manufacturing processes and design rules- Proven track record of successful tape-outs- Strong communication and collaboration abilitiesPreferred qualification - Experience in mentoring, leading, or managing more junior engineers- Experience with integration and verification in advanced nodes [5nm or below]- Knowledge of custom and digital design flows- Expertise with DFM (Design for Manufacturing) methodologies- Expertise in reliability verification (ESD, EM, IR drop)- Experience solving physical design challenges across various technologies such as DDR, PCIe, fabrics etc.- Experience in extraction of design parameters, QOR metrics, and analyzing trendsAmazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at .USA, CA, Cupertino - 183,000.00 - 247,600.00 USD annuallyUSA, TX, Austin - 159,200.00 - 215,300.00 USD annually
$100k
...seniorities.Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-... ...aggressive schedules.What We Need8+ years of top-level SOC physical design experience on complex, multi-million...SuggestedPermanent employment$183k - $247.6k
...their cloud services. We are seeking an experienced Sr. Physical Design STA Engineer to build the next generation of our cloud server platforms... ...• Develop & maintain flows for block and full-chip level static timing analysis • Write, debug & validate timing...SuggestedFull timeLocal areaFlexible hours$164.47k - $311.89k
...Details:Job Description: As a Physical Design Timing Engineer, you will play a pivotal... ...cutting-edge System-on-Chip (SoC) designs. Your expertise will... ...Responsibilities:Perform SOC level timing analysis and... ...plus factor in identifying top candidates. Requirements listed...SuggestedFull timeInternshipLocal areaImmediate startShift work- Hybrid // Physical Design Engineer-ASICs, SoCs, VLSI Physical Design Engineer-ASICs, SoCs, VLSI Full time Sunnyvale... ...: Key Responsibilities: Block-Level Physical Design: Floorplanning & Partitioning... ..., and leakage reduction techniques . Top-Level Physical Design: Chip-Level...SuggestedFull time
$183k - $247.6k
Annapurna Labs designs silicon and software that accelerates innovation. Customers... ...change the world.Custom SoCs (System on Chip) live at... ...Integrate multiple subsystems into top level SOC, ensure correct clock/... ...team members develop your engineering expertise so you feel...SuggestedLocal areaFlexible hours$141.91k - $200.34k
...About the RoleJoin the Design Technology Platform (DTP... ...as part of the X-Chip SoC Full-Chip Integration team... ...to the development of physical design methodologies... ...factor in identifying top candidates.Note: For information... ...s degree in electrical engineering or related field with...Full timeWork experience placementLocal areaImmediate startShift work$100k
...contributors of all seniorities. Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable,... ..., CO. We welcome candidates at various experience levels for this role. During the interview process, candidates...Permanent employmentFull time$250.6k - $375k
...Astera Labs (NASDAQ: ALAB) provides rack... ...seeking a VP of Physical Design to lead our critical... ...physical design engineers while establishing... ...connectivity Drive chip-level floorplanning,... ...to attract top physical design talent... ...of complex SoCs or ASICs ~ Proven...Full timeFlexible hours- ...SoC Physical Design Engineer, Electrical Analysis Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products... ...various electrical analyses at the block or chip level, including but not limited to Static/Dynamic IR, EM, Noise...
$183k - $247.6k
...Inferentia and Trainium SoCs that are used to... ...As a Sr. SoC Power Engineer, you ’ll contribute... ...at the ground level by modeling and estimating... ...every stage of the design from early RTL to... ...teams, and Physical Design experts - defining... ...measurements in the lab and correlate back...Local areaFlexible hours$168k - $264.5k
...looking for best-in-class Senior Physical Design Methodology Engineer, PPA Fusion Compiler to... ...of graphics processors and SOCs.Key responsibility includes... ...design approach, top-down design, budgeting, timing... ...,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,50...Full time$175k - $280k
...with the ultimate goal of enabling human life on Mars.SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)At SpaceX we’re leveraging our... ...Engineer/Senior: $175,000.00 - $280,000.00/per year Your actual level and base salary will be determined on a case-by-case...Permanent employmentTemporary workWorldwideWeekend work$140k - $229.8k
Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:... ...ASIC Team is actively seeking candidates for several physical design engineering positions in our SOC and core design team. As a physical design engineer...Work experience placementWork from home$164.47k - $269.1k
...About the RoleAs a Senior SoC Design Verification Engineer, you will lead verification... ...block, subsystem, and SoC-level verification environments.... ...developers, post-silicon teams, and physical design teams to enhance... ...plus factor in identifying top candidates.For information...Full timeLocal areaImmediate startWorldwideShift work$209k - $250k
...Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure... ...an Astera Labs Principal Physical Design Engineer (STA) you will play a... ...robust timing across complex SoCs. Develop and validate SDC... ...at both block and full-chip levels, including root cause analysis...Full timeFlexible hours$185k - $240k
...Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure... ...As a Principal Physical Design Engineer - Methodology , you will define... ...flow development for complex SoCs at advanced nodes (7nm and below... ...ICC2) toolchains ~ Expert-level scripting ability in Python,...Full timeFlexible hours$184.7k - $324.8k
...SoC Physical Design Engineer, PnR Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services... ...relevant industry experience Experience with partition level P&R implementation including floorplanning, clock and power...Relocation$183k - $247.6k
..., or a PhD with 4+ years in Electrical Engineering or Computer Science. We need strong... ...similar. We need an understanding of ASIC physical design from RTL to GDSII. We require... ...Quantus. Preferred: We value circuit-level analysis experience using tools like SPICE...Full time- Qualcomm Atheros, Inc. is seeking a physical design engineer to join our Connectivity SoC team. You will contribute to the complete physical design flow for complex, high‑speed, low‑power designs, including floorplanning, placement, routing, and timing closure. Candidates...
$220.92k - $311.89k
...highly experienced a Director, SoC Design Engineering, to lead the functional... ...execute block, subsystem, and SoC-level verification plans,... ...Foundry Enablement (supporting top customers and validating technologies... ...origin, ancestry, age, physical or mental disability,...Full timeWork experience placementLocal areaImmediate startWorldwideShift workNight shift$160k - $200k
...Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through... ...is non-negotiable in the SoCs we ship. As a Technical Lead Physical Design Engineer- Power Integrity , you will own... ...analysis at block and full-chip levels, driving closure to foundry sign-...Full timeFlexible hours$120k - $220k
...will fundamentally change the design, economics, manufacturing... ...a highly experienced Senior Physical Design Engineer to join our ASIC implementation... ...of complex digital SoC designs from netlist to GDSII... ...compilers, and analog IP into top-level designs • Analyze and optimize...Full timeWork at officeImmediate startVisa sponsorshipNight shift$183k - $247.6k
...develops the Inferentia and Trainium SOCs that are used to power today’s AI workloads... .... We are seeking experienced Design Verification Engineers to build the next generation of our cloud... ...Verify custom chip designs at the SOC level- Integrate 3rd party IPs and VIPs into...Local areaWork from homeFlexible hours$138k - $197k
...microarchitecture for digital designs within the TPU.... ...Register Transfer Level (RTL) code,... ...closely with the Physical Design team to... ...degree in Electrical Engineering, Computer Engineering... ....Experience with SOC implementation... ...You will work on top-level RTL, architecture...Worldwide$157.3k - $212.8k
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning... ...you’ll be responsible for the design and optimization of hardware... ...re looking for an ASIC Design Engineer to help us trail-blaze new... ...accelerator engines, debug and system level architectures- Have a strong...InternshipLocal areaWork from homeFlexible hours$120k - $250k
...models run as efficiently as allowed by physics, bringing the world years ahead in AI... ...availability. MatX is seeking silicon physical design engineers to join our team as we create best-in-... ...subsystems or subsets and/or chip-level Physical Design deliverables including...Full timeWork experience placementLocal areaRemote workMonday to FridayFlexible hours$230k - $280k
...works with the leading model labs, global enterprises, and cutting... ...a member of our tight knit physical design team, you will be working on... ...combination of traditional ASIC/SoC physical design skills,... ...experience.Strong knowledge of block level and full-chip physical...$136k - $218.5k
NVIDIA is looking for a Senior SOC Design Engineer to join our SOC Design team! At NVIDIA, you'll... ...partnering with experts in ASIC design, Physical design, CAD, Package Design, Software,... ...GPUs and SOCsDevelop and refine system-level methodologies and tools for efficient SOC...Full time$116k - $166k
Participate in the Physical Design (PD) of blocks for complex TPU chips.Contribute to... ...qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer... ...(CTS).Experience in block/subchip level place and route for SoC or with multiple-cycles of SoC in...Worldwide$168k - $264.5k
...impact on the world.We are looking for a physical design engineer to be a part of NVIDIA’s physical... ...implementation of GPU, CPU, Network processors and SOC, with emphasis on PPA (Power,... ...range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level...Full timeRemote work
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