Senior Testchip SoC Physical Design Engineer (Integration & Methodology)

Job Details:Job Description: About the RoleJoin the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness.In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.What You’ll DoKey responsibilities will include but not limited to:Developing layout design methodology for testchip development in next generation process nodesWorking closely with Process Integration, Yield and QnR to define critical Design features that need to be exercised in the early lead vehicle test chips.Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integrationBuilding and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements by working closely with PDK teamsDriving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification toolsWorking with tool/flow owners and vendors for ongoing tool/methodology improvementBehavioral traits that we are looking for:Exhibiting strong interest in Layout design in advanced technology nodes. Strong verbal and written communication skillsAbility to work well both autonomously and in an intensive, cooperative team environmentCoordinate between different stakeholders for testchip to arrive at execution commit for testchipMotivation to continuously learn and drive to push improved layout productivity and efficiencyWhy Join UsWork on cutting-edge semiconductor technologies that shape the future of computingCollaborate with industry-leading experts across design and manufacturingOpportunities for career growth and technical leadershipContribute to innovations that impact global technology at scaleIntel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life See Intel Benefits for more details. Qualifications:Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Note: For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship InformationMinimum Qualifications and Experience:Master's degree in electrical engineering or related field with minimum of 5 years of experience in the following areas:Experience with physical/layout design in advance technology nodesIn Layout design tools like Cadence Virtuoso Suite or Synopsys Custom CompilerDesign rules and layout constraints in advanced semiconductor processesExperience with floorplanning, hierarchical design integration, and layout verification/debugPreferred Qualifications and Experience:Experience in Definition of Testchip/Product design from Concept to Execution CommitExperience in working with Foundry teams on negotiating features to exercise in designProven Project Management skills on coordinating and tracking the entire design cycle of a project from Feature definition to final Tape-inPrevious related work experience in a semiconductor foundry preferredJob Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, California, Santa Clara, US, Texas, AustinPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.SummaryLocation: US, Oregon, Hillsboro; US, California, Santa Clara; US, Texas, AustinType: Full time