Senior Design Verification Engineer

Job Overview

Altera is responsible for High-Speed Protocol IP development, which includes participating in high-level product specifications, logic/RTL design and implementation, RTL verification, IP FPGA validation and debugging. As Lead DV Engineer focusing on IP Verification & Validation, you will carry out design validation for Altera next generation IP's across the Altera FPGA IP product portfolios.

Responsibilities

• Verify and validate IP for robust functionality from functional simulation.
• Create comprehensive verification and validation plans based on IP/FPGA architecture specifications.
• Develop IP/subsystem/system level testbenches and create tests, and necessary coverage goals based on specification to verify the implementation.
• Write directed and random test cases, debug failures, file and close bugs.
• Review verification and validation results against coverage goals, write, analyze, and achieve coverage metrics.
• Collaborate with cross‑functional teams and prepare/support IP functional validation tests for IP bring‑up on actual FPGA development kits.
• Create and establish IP subsystem/solution validation coverage strategy and standardized framework.
• Drive system test design implementation and overall IP system validation on hardware, maximizing FPGA hardware capability to bring substantial improvement to IP quality & usability.
• Develop verification and validation tools and flows, as needed.
• Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time‑to‑market.

Salary Range

The pay range for Bay Area California only is $142.6k - $206.5k USD. Actual salary may vary based on a number of factors including job location, job‑related knowledge, skills, experience, training, etc. Incentive opportunities that reward employees based on individual and company performance are also offered.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering or a closely related field and 9+ years of industry experience.
• 9+ years of experience developing verification collateral in Verilog, System Verilog and UVM.
• 7+ years with Ethernet/PCIe/CXL protocol verification.
• 7+ years with UVM fluency and 7+ years of complex coverage‑driven random constraint UVM environments.
• 7+ years of experience with high‑level specification into test plan and developing test cases.
• 7+ years of debugging skills to narrow down and isolate issues between RTL design and testbench or test case.
• Good communication skills.

Job Type & Location

Regular – Shift 1 – United States of America – Primary Location: San Jose, California, United States.

Additional Information

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.