Senior Analog Layout Engineer for SoC IPs (FinFET)
$97.7k - $203.8kCapgemini
Capgemini is seeking an experienced Analog / RF Layout Designer to provide onsite support for advanced semiconductor nodes. In this role, you will develop complex analog and mixed-signal IP, working collaboratively with global teams. The ideal candidate will have extensive experience in layout design, focusing on deep sub-micron and FinFET technologies. Benefits include comprehensive medical coverage, paid time off, and a competitive salary range of $97,700 to $203,800. #J-18808-Ljbffr Capgemini
Vacancy posted 6 hours ago
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