DFT Engineer (CE-TBD)

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end‑user solutions for the world’s top consumer brands. Cirrus Logic is also known for its award‑winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! As a DFT engineer in our mixed signal audio development team, you will be performing initial test planning, inserting memory BIST and scan, improving coverage, and delivering test patterns to our product test group. You will be working on industry leading mixed‑signal SoC’s for consumer mobile audio markets, supporting several expanding product lines. Responsibilities Work within a collaborative team environment to define, implement, and review DFT features. You will generate, insert, and verify Memory BIST logic. Perform scan insertion and ATPG pattern generation. Help develop and review DFT timing and equivalence checking constraints. Perform MBIST and ATPG pattern verification with gate level simulations. Identify and improve any test coverage gaps. Perform test cost planning and analysis. Deliver MBIST and ATPG patterns to the product test group and support silicon bring‑up on the ATE. Required Skills and Qualifications MSEE with 2+ years of experience or BS with relevant industry experience. Possess strong hands‑on working knowledge on ASIC DFT design and verification. Experience in industry standard EDA tools for DFT such as FastScan, TestKompress, TetraMAX, Test Compiler etc. Preferred Skills and Qualifications Experience with Verilog, System Verilog, or VHDL. Understanding of low power test techniques and architectures. Knowledge of scripting languages such as Perl, Python, or TCL. Experience with synthesis, static timing analysis, and developing timing constraints. Strong oral and written communication skills. Experience with flows and automation. Work independently as well as part of a team. Have a curious and inquiring mind with the commitment to follow through on getting answers. Experience with debugging and root causing silicon problems. Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role. Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job‑related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law. #J-18808-Ljbffr Cirrus Logic